10f200: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB INTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config INTRC_OSC & CP_OFF & WDT_ON & MCLRE_OFF 10f202: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB INTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config INTRC_OSC & CP_OFF & WDT_ON & MCLRE_OFF 10f204: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB INTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config INTRC_OSC & CP_OFF & WDT_ON & MCLRE_OFF 10f206: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB INTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config INTRC_OSC & CP_OFF & WDT_ON & MCLRE_OFF 10f220: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB MCPU_ON EQU 0X0FFD MCPU_OFF EQU 0X0FFF IOFSCS_8MHZ EQU 0X0FFF IOFSCS_4MHZ EQU 0X0FFE IOSCFS_8MHZ EQU 0X0FFF IOSCFS_4MHZ EQU 0X0FFE @ CONFIG_REQ @ __config IOFSCS_4MHZ & CP_OFF & WDT_ON & MCLRE_OFF & MCPU_OFF 10f222: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB MCPU_ON EQU 0X0FFD MCPU_OFF EQU 0X0FFF IOFSCS_8MHZ EQU 0X0FFF IOFSCS_4MHZ EQU 0X0FFE IOSCFS_8MHZ EQU 0X0FFF IOSCFS_4MHZ EQU 0X0FFE @ CONFIG_REQ @ __config IOFSCS_4MHZ & CP_OFF & WDT_ON & MCLRE_OFF & MCPU_OFF 12c508: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD INTRC_OSC EQU 0X0FFE EXTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & MCLRE_OFF 12c508a: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD INTRC_OSC EQU 0X0FFE EXTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & MCLRE_OFF 12c509: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD INTRC_OSC EQU 0X0FFE EXTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & MCLRE_OFF 12c509a: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD INTRC_OSC EQU 0X0FFE EXTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & MCLRE_OFF 12c671: MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3F7F CP_ALL EQU 0X009F CP_75 EQU 0X15BF CP_50 EQU 0X2ADF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA INTRC_OSC EQU 0X3FFC INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC EQU 0X3FFE EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & CP_OFF & MCLRE_ON 12c672: MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3F7F CP_ALL EQU 0X009F CP_75 EQU 0X15BF CP_50 EQU 0X2ADF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA INTRC_OSC EQU 0X3FFC INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC EQU 0X3FFE EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & CP_OFF & MCLRE_ON 12ce518: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD INTRC_OSC EQU 0X0FFE EXTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & MCLRE_OFF 12ce519: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD INTRC_OSC EQU 0X0FFE EXTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & MCLRE_OFF 12ce673: MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3F7F CP_ALL EQU 0X009F CP_75 EQU 0X15BF CP_50 EQU 0X2ADF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA INTRC_OSC EQU 0X3FFC INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC EQU 0X3FFE EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & CP_OFF & MCLRE_ON 12ce674: MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3F7F CP_ALL EQU 0X009F CP_75 EQU 0X15BF CP_50 EQU 0X2ADF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA INTRC_OSC EQU 0X3FFC INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC EQU 0X3FFE EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & CP_OFF & MCLRE_ON 12f508: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD INTRC_OSC EQU 0X0FFE EXTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & MCLRE_OFF 12f509: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD INTRC_OSC EQU 0X0FFE EXTRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & MCLRE_OFF 12f510: IOSCFS_ON EQU 0X0FFF IOSCFS_OFF EQU 0X0FDF MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FEF CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD IntRC_OSC EQU 0X0FFE ExtRC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config IOSCFS_OFF & MCLRE_ON & XT_OSC & WDT_ON & CP_OFF 12f629: CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF CP_ON EQU 0X3F7F CP_OFF EQU 0X3FFF BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & CP_OFF & MCLRE_ON 12f635: WUREN_ON EQU 0X2FFF WUREN_OFF EQU 0X3FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & CP_OFF & CPD_OFF & MCLRE_ON & BOD_OFF & WUREN_OFF & FCMEN_OFF & IESO_OFF 12f675: CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF CP_ON EQU 0X3F7F CP_OFF EQU 0X3FFF BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & CP_OFF & MCLRE_ON 12f683: FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD INTOSC EQU 0X3FFD INTOSCIO EQU 0X3FFC EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF EXTRC EQU 0X3FFF EXTRCIO EQU 0X3FFE @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & CP_OFF & MCLRE_ON 16c54: CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c54a: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c54b: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c54c: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c55: CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c55a: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c56: CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c56a: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c57: CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c57c: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c58a: CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16c61: CP_ON EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FFF PWRTE_OFF EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c62: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c62a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c62b: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c63: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c63a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c64: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c64a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c65: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c65a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c65b: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c66: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c67: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c71: CP_ON EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FFF PWRTE_OFF EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c71a: CP_ON EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FFF PWRTE_OFF EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c72: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c72a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c73: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c73a: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c73b: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c73c: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c74: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c74a: CP_ALL EQU 0X3F8F CP_75 EQU 0X3F9F CP_50 EQU 0X3FAF CP_OFF EQU 0X3FBF PWRTE_ON EQU 0X3FBF PWRTE_OFF EQU 0X3FB7 WDT_ON EQU 0X3FBF WDT_OFF EQU 0X3FBB LP_OSC EQU 0X3FBC XT_OSC EQU 0X3FBD HS_OSC EQU 0X3FBE RC_OSC EQU 0X3FBF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c76: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c77: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c84: CP_ON EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FFF PWRTE_OFF EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c505: MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FDF CP_ON EQU 0X002F CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FF7 LP_OSC EQU 0X0FF8 XT_OSC EQU 0X0FF9 HS_OSC EQU 0X0FFA IntRC_OSC_RB4EN EQU 0X0FFC IntRC_OSC_CLKOUTEN EQU 0X0FFD ExtRC_OSC_RB4EN EQU 0X0FFE ExtRC_OSC_CLKOUTEN EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON & ExtRC_OSC_CLKOUTEN 16c554: CP_ON EQU 0X00CF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c554a: CP_ON EQU 0X00CF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c558: CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c558a: CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16c620: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ON EQU 0X00CF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c620a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ON EQU 0X00CF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c621: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_50 EQU 0X15DF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c621a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_50 EQU 0X15DF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c622: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c622a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c641: CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MPEEN_ON EQU 0X3FFF MPEEN_OFF EQU 0X3F7F @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & MPEEN_OFF & BODEN_OFF 16c642: CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MPEEN_ON EQU 0X3FFF MPEEN_OFF EQU 0X3F7F @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & MPEEN_OFF & BODEN_OFF 16c661: CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MPEEN_ON EQU 0X3FFF MPEEN_OFF EQU 0X3F7F @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & MPEEN_OFF & BODEN_OFF 16c662: CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MPEEN_ON EQU 0X3FFF MPEEN_OFF EQU 0X3F7F @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & MPEEN_OFF & BODEN_OFF 16c710: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ON EQU 0X004F CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c711: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ON EQU 0X004F CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c712: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c715: MPEEN_ON EQU 0X3FFF MPEEN_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_50 EQU 0X15DF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & MPEEN_OFF & BODEN_OFF 16c716: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c745: CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB HS_OSC EQU 0X3FFC EC_OSC EQU 0X3FFD H4_OSC EQU 0X3FFE E4_OSC EQU 0X3FFF @ CONFIG_REQ @ __config H4_OSC & WDT_ON & PWRTE_ON & CP_OFF 16c765: CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB HS_OSC EQU 0X3FFC EC_OSC EQU 0X3FFD H4_OSC EQU 0X3FFE E4_OSC EQU 0X3FFF @ CONFIG_REQ @ __config H4_OSC & WDT_ON & PWRTE_ON & CP_OFF 16c770: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X0CFF CP_OFF EQU 0X3FFF VBOR_25 EQU 0X3FFF VBOR_27 EQU 0X3BFF VBOR_42 EQU 0X37FF VBOR_45 EQU 0X33FF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF MCLRE_OFF EQU 0X3FDF MCLRE_ON EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 ER_OSC_CLKOUT EQU 0X3FFF ER_OSC_NOCLKOUT EQU 0X3FFE INTRC_OSC_CLKOUT EQU 0X3FFD INTRC_OSC_NOCLKOUT EQU 0X3FFC EXTCLK_OSC EQU 0X3FFB HS_OSC EQU 0X3FFA XT_OSC EQU 0X3FF9 LP_OSC EQU 0X3FF8 @ CONFIG_REQ @__config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c771: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X0CFF CP_OFF EQU 0X3FFF VBOR_25 EQU 0X3FFF VBOR_27 EQU 0X3BFF VBOR_42 EQU 0X37FF VBOR_45 EQU 0X33FF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF MCLRE_OFF EQU 0X3FDF MCLRE_ON EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 ER_OSC_CLKOUT EQU 0X3FFF ER_OSC_NOCLKOUT EQU 0X3FFE INTRC_OSC_CLKOUT EQU 0X3FFD INTRC_OSC_NOCLKOUT EQU 0X3FFC EXTCLK_OSC EQU 0X3FFB HS_OSC EQU 0X3FFA XT_OSC EQU 0X3FF9 LP_OSC EQU 0X3FF8 @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c773: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X0CCF CP_75 EQU 0X1DDF CP_50 EQU 0X2EEF CP_OFF EQU 0X3FFF VBOR_25 EQU 0X3FFF VBOR_27 EQU 0X3BFF VBOR_42 EQU 0X37FF VBOR_45 EQU 0X33FF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @__config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16c774: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X0CCF CP_75 EQU 0X1DDF CP_50 EQU 0X2EEF CP_OFF EQU 0X3FFF VBOR_25 EQU 0X3FFF VBOR_27 EQU 0X3BFF VBOR_42 EQU 0X37FF VBOR_45 EQU 0X33FF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16ce625: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X00CF CP_75 EQU 0X15DF CP_50 EQU 0X2AEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16cr56: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16cr57a: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16cr57b: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16cr58a: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16cr58b: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16cr58c: CP_ON EQU 0X0007 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16cr84: CP_ON EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FFF PWRTE_OFF EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16cr620a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ON EQU 0X00CF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON & BODEN_OFF 16f54: CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16f57: CP_ON EQU 0X0FF7 CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FFB LP_OSC EQU 0X0FFC XT_OSC EQU 0X0FFD HS_OSC EQU 0X0FFE RC_OSC EQU 0X0FFF @ CONFIG_REQ @ __config XT_OSC & CP_OFF & WDT_ON 16f72: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & BODEN_ON & CP_OFF 16f73: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & BODEN_ON & CP_OFF 16f74: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & BODEN_ON & CP_OFF 16f76: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & BODEN_ON & CP_OFF 16f77: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & BODEN_ON & CP_OFF 16f83: CP_ON EQU 0X000F CP_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16f84: CP_ON EQU 0X000F CP_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16f84a: CP_ON EQU 0X000F CP_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & PWRTE_ON & CP_OFF & WDT_ON 16f87: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ;Configuration Byte1 Options CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF CCP1_RB0 EQU 0X3FFF CCP1_RB3 EQU 0X2FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF WRT_PROTECT_OFF EQU 0X3FFF WRT_PROTECT_256 EQU 0X3DFF WRT_PROTECT_2048 EQU 0X3BFF WRT_PROTECT_ALL EQU 0X39FF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MCLR_ON EQU 0X3FFF MCLR_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB EXTRC_CLKOUT EQU 0X3FFF EXTRC_IO EQU 0X3FFE INTRC_CLKOUT EQU 0X3FFD INTRC_IO EQU 0X3FFC EXTCLK EQU 0X3FEF HS_OSC EQU 0X3FEE XT_OSC EQU 0X3FED LP_OSC EQU 0X3FEC ;Configuration Byte2 Options IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3FFD FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X3FFE @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & PWRTE_ON & WRT_PROTECT_OFF & CP_OFF & CPD_OFF & DEBUG_ON 16f88: ; [START OF CONFIGURATION BITS] _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ;Configuration Byte1 Options CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF CCP1_RB0 EQU 0X3FFF CCP1_RB3 EQU 0X2FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF WRT_PROTECT_OFF EQU 0X3FFF WRT_PROTECT_256 EQU 0X3DFF WRT_PROTECT_2048 EQU 0X3BFF WRT_PROTECT_ALL EQU 0X39FF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MCLR_ON EQU 0X3FFF MCLR_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB EXTRC_CLKOUT EQU 0X3FFF EXTRC_IO EQU 0X3FFE INTRC_CLKOUT EQU 0X3FFD INTRC_IO EQU 0X3FFC EXTCLK EQU 0X3FEF HS_OSC EQU 0X3FEE XT_OSC EQU 0X3FED LP_OSC EQU 0X3FEC ;Configuration Byte2 Options IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3FFD FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X3FFE @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & PWRTE_ON & WRT_PROTECT_OFF & CP_OFF & CPD_OFF & DEBUG_ON 16f506: IOSCFS_ON EQU 0X0FFF IOSCFS_OFF EQU 0X0FBF MCLRE_ON EQU 0X0FFF MCLRE_OFF EQU 0X0FDF CP_ON EQU 0X0FEF CP_OFF EQU 0X0FFF WDT_ON EQU 0X0FFF WDT_OFF EQU 0X0FF7 LP_OSC EQU 0X0FF8 XT_OSC EQU 0X0FF9 HS_OSC EQU 0X0FFA EC_OSC EQU 0X0FFB IntRC_OSC_RB4EN EQU 0X0FFC IntRC_OSC_CLKOUTEN EQU 0X0FFD ExtRC_OSC_RB4EN EQU 0X0FFE ExtRC_OSC_CLKOUTEN EQU 0X0FFF @ CONFIG_REQ @ __config MCLRE_ON & XT_OSC & WDT_ON & CP_OFF & IOSCFS_OFF 16f616: BOR_ON EQU 0X3FFF BOR_NSLEEP EQU 0X3EFF BOR_OFF EQU 0X3CFF IOSCFS_8MHZ EQU 0X3FFF IOSCFS_4MHZ EQU 0X3F7F CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config IOSCFS_4MHZ & MCLRE_ON & XT_OSC & WDT_ON & PWRTE_ON & BOR_ON & CP_OFF 16f627: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X03FF CP_75 EQU 0X17FF CP_50 EQU 0X2BFF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF ER_OSC_CLKOUT EQU 0X3FFF ER_OSC_NOCLKOUT EQU 0X3FFE INTRC_OSC_CLKOUT EQU 0X3FFD INTRC_OSC_NOCLKOUT EQU 0X3FFC EXTCLK_OSC EQU 0X3FEF LP_OSC EQU 0X3FEC XT_OSC EQU 0X3FED HS_OSC EQU 0X3FEE @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & MCLRE_ON 16f627a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ON EQU 0X1FFF CP_OFF EQU 0X3FFF DATA_CP_ON EQU 0X3EFF DATA_CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF RC_OSC_CLKOUT EQU 0X3FFF RC_OSC_NOCLKOUT EQU 0X3FFE INTRC_OSC_CLKOUT EQU 0X3FFD INTRC_OSC_NOCLKOUT EQU 0X3FFC EXTCLK_OSC EQU 0X3FEF LP_OSC EQU 0X3FEC XT_OSC EQU 0X3FED HS_OSC EQU 0X3FEE @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & MCLRE_ON & DATA_CP_OFF 16f628: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X03FF CP_75 EQU 0X17FF CP_50 EQU 0X2BFF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF ER_OSC_CLKOUT EQU 0X3FFF ER_OSC_NOCLKOUT EQU 0X3FFE INTRC_OSC_CLKOUT EQU 0X3FFD INTRC_OSC_NOCLKOUT EQU 0X3FFC EXTCLK_OSC EQU 0X3FEF LP_OSC EQU 0X3FEC XT_OSC EQU 0X3FED HS_OSC EQU 0X3FEE @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & MCLRE_ON 16f628a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ON EQU 0X1FFF CP_OFF EQU 0X3FFF DATA_CP_ON EQU 0X3EFF DATA_CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF RC_OSC_CLKOUT EQU 0X3FFF RC_OSC_NOCLKOUT EQU 0X3FFE INTRC_OSC_CLKOUT EQU 0X3FFD INTRC_OSC_NOCLKOUT EQU 0X3FFC EXTCLK_OSC EQU 0X3FEF LP_OSC EQU 0X3FEC XT_OSC EQU 0X3FED HS_OSC EQU 0X3FEE @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & MCLRE_ON & DATA_CP_OFF 16f630: CPD EQU 0X3EFF CPD_OFF EQU 0X3FFF CP EQU 0X3F7F CP_OFF EQU 0X3FFF BODEN EQU 0X3FFF BODEN_OFF EQU 0X3FBF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & CP_OFF & CPD_OFF & MCLRE_ON 16f636: WUREN_ON EQU 0X2FFF WUREN_OFF EQU 0X3FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config WUREN_OFF & FCMEN_OFF & MCLRE_ON & XT_OSC & WDT_ON & PWRTE_ON & BOD_ON & CP_OFF & CPD_OFF 16f639: WUREN_ON EQU 0X2FFF WUREN_OFF EQU 0X3FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config WUREN_OFF & FCMEN_OFF & MCLRE_ON & XT_OSC & WDT_ON & PWRTE_ON & BOD_ON & CP_OFF & CPD_OFF 16f648a: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ON EQU 0X1FFF CP_OFF EQU 0X3FFF DATA_CP_ON EQU 0X3EFF DATA_CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF RC_OSC_CLKOUT EQU 0X3FFF RC_OSC_NOCLKOUT EQU 0X3FFE INTRC_OSC_CLKOUT EQU 0X3FFD INTRC_OSC_NOCLKOUT EQU 0X3FFC EXTCLK_OSC EQU 0X3FEF LP_OSC EQU 0X3FEC XT_OSC EQU 0X3FED HS_OSC EQU 0X3FEE @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & MCLRE_ON & DATA_CP_OFF 16f676: CPD EQU 0X3EFF CPD_OFF EQU 0X3FFF CP EQU 0X3F7F CP_OFF EQU 0X3FFF BODEN EQU 0X3FFF BODEN_OFF EQU 0X3FBF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & CP_OFF & CPD_OFF & MCLRE_ON 16f684: FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF BODEN_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & CP_OFF & CPD_OFF & MCLRE_ON & FCMEN_OFF & IESO_OFF 16f685: FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & CP_OFF & CPD_OFF & MCLRE_ON & FCMEN_OFF & IESO_OFF 16f687: FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & CP_OFF & CPD_OFF & MCLRE_ON & FCMEN_OFF & IESO_OFF 16f688: FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF BODEN_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & CP_OFF & CPD_OFF & MCLRE_ON & FCMEN_OFF & IESO_OFF 16f689: FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & CP_OFF & CPD_OFF & MCLRE_ON & FCMEN_OFF & IESO_OFF 16f690: FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & CP_OFF & CPD_OFF & MCLRE_ON & FCMEN_OFF & IESO_OFF 16f716: BODEN_ON EQU 0X3FFF ; C712/C716 compatibility BODEN_OFF EQU 0X3FBF ; C712/C716 compatibility BOREN_ON EQU 0X3FFF BOREN_OFF EQU 0X3FBF VBOR_25 EQU 0X3F7F VBOR_40 EQU 0X3FFF CP_ON EQU 0X1FFF CP_ALL EQU 0X1FFF ; C712/C716 compatibility CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOREN_ON & VBOR_25 & CP_OFF 16f737: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ;Configuration Byte 1 Options CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF CCP2_RC1 EQU 0X3FFF CCP2_RB3 EQU 0X2FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF VBOR_2_0 EQU 0X3FFF VBOR_2_7 EQU 0X3F7F VBOR_4_2 EQU 0X3EFF VBOR_4_5 EQU 0X3E7F BOREN_1 EQU 0X3FFF ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) BOREN_0 EQU 0X3FBF ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) MCLR_ON EQU 0X3FFF MCLR_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB EXTRC_CLKOUT EQU 0X3FFF EXTRC_IO EQU 0X3FFE INTRC_CLKOUT EQU 0X3FFD INTRC_IO EQU 0X3FFC EXTCLK EQU 0X3FEF HS_OSC EQU 0X3FEE XT_OSC EQU 0X3FED LP_OSC EQU 0X3FEC ;Configuration Byte 2 Options BORSEN_1 EQU 0X3FFF ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) BORSEN_0 EQU 0X3FBF ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3FFD FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X3FFE ;**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) ;BOREN_1 & BORSEN_1 = BOR enabled and always on ;BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware ;BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) ;BOREN_0 & BORSEN_0 = BOR disabled @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & PWRTE_ON & CCP2_RC1 & BOREN_0 & PWRTE_ON & CP_OFF & DEBUG_ON 16f747: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ;Configuration Byte 1 Options CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF CCP2_RC1 EQU 0X3FFF CCP2_RB3 EQU 0X2FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF VBOR_2_0 EQU 0X3FFF VBOR_2_7 EQU 0X3F7F VBOR_4_2 EQU 0X3EFF VBOR_4_5 EQU 0X3E7F BOREN_1 EQU 0X3FFF ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) BOREN_0 EQU 0X3FBF ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) MCLR_ON EQU 0X3FFF MCLR_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB EXTRC_CLKOUT EQU 0X3FFF EXTRC_IO EQU 0X3FFE INTRC_CLKOUT EQU 0X3FFD INTRC_IO EQU 0X3FFC EXTCLK EQU 0X3FEF HS_OSC EQU 0X3FEE XT_OSC EQU 0X3FED LP_OSC EQU 0X3FEC ;Configuration Byte 2 Options BORSEN_1 EQU 0X3FFF ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) BORSEN_0 EQU 0X3FBF ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3FFD FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X3FFE ;**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) ;BOREN_1 & BORSEN_1 = BOR enabled and always on ;BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware ;BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) ;BOREN_0 & BORSEN_0 = BOR disabled @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & PWRTE_ON & CCP2_RC1 & BOREN_0 & PWRTE_ON & CP_OFF & DEBUG_ON 16f767: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ;Configuration Byte 1 Options CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF CCP2_RC1 EQU 0X3FFF CCP2_RB3 EQU 0X2FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF VBOR_2_0 EQU 0X3FFF VBOR_2_7 EQU 0X3F7F VBOR_4_2 EQU 0X3EFF VBOR_4_5 EQU 0X3E7F BOREN_1 EQU 0X3FFF ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) BOREN_0 EQU 0X3FBF ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) MCLR_ON EQU 0X3FFF MCLR_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB EXTRC_CLKOUT EQU 0X3FFF EXTRC_IO EQU 0X3FFE INTRC_CLKOUT EQU 0X3FFD INTRC_IO EQU 0X3FFC EXTCLK EQU 0X3FEF HS_OSC EQU 0X3FEE XT_OSC EQU 0X3FED LP_OSC EQU 0X3FEC ;Configuration Byte 2 Options BORSEN_1 EQU 0X3FFF ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) BORSEN_0 EQU 0X3FBF ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3FFD FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X3FFE ;**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) ;BOREN_1 & BORSEN_1 = BOR enabled and always on ;BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware ;BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) ;BOREN_0 & BORSEN_0 = BOR disabled @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & PWRTE_ON & CCP2_RC1 & BOREN_0 & PWRTE_ON & CP_OFF & DEBUG_ON 16f777: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ;Configuration Byte 1 Options CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF CCP2_RC1 EQU 0X3FFF CCP2_RB3 EQU 0X2FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF VBOR_2_0 EQU 0X3FFF VBOR_2_7 EQU 0X3F7F VBOR_4_2 EQU 0X3EFF VBOR_4_5 EQU 0X3E7F BOREN_1 EQU 0X3FFF ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) BOREN_0 EQU 0X3FBF ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) MCLR_ON EQU 0X3FFF MCLR_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB EXTRC_CLKOUT EQU 0X3FFF EXTRC_IO EQU 0X3FFE INTRC_CLKOUT EQU 0X3FFD INTRC_IO EQU 0X3FFC EXTCLK EQU 0X3FEF HS_OSC EQU 0X3FEE XT_OSC EQU 0X3FED LP_OSC EQU 0X3FEC ;Configuration Byte 2 Options BORSEN_1 EQU 0X3FFF ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) BORSEN_0 EQU 0X3FBF ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3FFD FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X3FFE ;**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) ;BOREN_1 & BORSEN_1 = BOR enabled and always on ;BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware ;BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) ;BOREN_0 & BORSEN_0 = BOR disabled @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & PWRTE_ON & CCP2_RC1 & BOREN_0 & PWRTE_ON & CP_OFF & DEBUG_ON 16f785: FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF BOR_ON EQU 0X3FFF BOR_NSLEEP EQU 0X3EFF BOR_SBOREN EQU 0X3DFF BOR_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FEF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config FCMEN_OFF & IESO_OFF & MCLRE_ON & BOD_OFF & XT_OSC & WDT_ON & PWRTE_ON & BOR_ON & CP_OFF & CPD_OFF 16f818: CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF CCP1_RB2 EQU 0X3FFF CCP1_RB3 EQU 0X2FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF WRT_ENABLE_OFF EQU 0X3FFF WRT_ENABLE_512 EQU 0X3DFF WRT_ENABLE_1024 EQU 0X3BFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB EXTRC_CLKOUT EQU 0X3FFF EXTRC_IO EQU 0X3FFE INTRC_CLKOUT EQU 0X3FFD INTRC_IO EQU 0X3FFC EXTCLK EQU 0X3FEF HS_OSC EQU 0X3FEE XT_OSC EQU 0X3FED LP_OSC EQU 0X3FEC @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & CPD_OFF & MCLRE_ON & WRT_ENABLE_1024 & DEBUG_ON 16f819: CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF CCP1_RB2 EQU 0X3FFF CCP1_RB3 EQU 0X2FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF WRT_ENABLE_OFF EQU 0X3FFF WRT_ENABLE_512 EQU 0X3DFF WRT_ENABLE_1024 EQU 0X3BFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB EXTRC_CLKOUT EQU 0X3FFF EXTRC_IO EQU 0X3FFE INTRC_CLKOUT EQU 0X3FFD INTRC_IO EQU 0X3FFC EXTCLK EQU 0X3FEF HS_OSC EQU 0X3FEE XT_OSC EQU 0X3FED LP_OSC EQU 0X3FEC @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & CPD_OFF & MCLRE_ON & DEBUG_ON 16f870: CP_ALL EQU 0X0FCF CP_HALF EQU 0X1FDF CP_UPPER_256 EQU 0X2FEF CP_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF DEBUG_OFF EQU 0X3FFF WRTE_ON EQU 0X3FFF WRTE_OFF EQU 0X3DFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & WRTE_ON & CP_OFF & DEBUG_ON 16f871: CP_ALL EQU 0X0FCF CP_HALF EQU 0X1FDF CP_UPPER_256 EQU 0X2FEF CP_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF DEBUG_OFF EQU 0X3FFF WRTE_ON EQU 0X3FFF WRTE_OFF EQU 0X3DFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & WRTE_ON & CP_OFF & DEBUG_ON 16f872: CP_ALL EQU 0X0FCF CP_HALF EQU 0X1FDF CP_UPPER_256 EQU 0X2FEF CP_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF DEBUG_OFF EQU 0X3FFF WRTE_ON EQU 0X3FFF WRTE_OFF EQU 0X3DFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & WRTE_ON & CP_OFF & DEBUG_ON 16f873: CP_ALL EQU 0X0FCF CP_HALF EQU 0X1FDF CP_UPPER_256 EQU 0X2FEF CP_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF DEBUG_OFF EQU 0X3FFF WRTE_ON EQU 0X3FFF WRTE_OFF EQU 0X3DFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & WRTE_ON & CP_OFF & DEBUG_ON 16f873a: CP_ALL EQU 0X3FFF CP_OFF EQU 0X1FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF WRT_OFF EQU 0X3FFF ; No prog memmory write protection WRT_256 EQU 0X3DFF ; First 256 prog memmory write protected WRT_1FOURTH EQU 0X3BFF ; First quarter prog memmory write protected WRT_HALF EQU 0X39FF ; First half memmory write protected CPD_OFF EQU 0X3FFF CPD_ON EQU 0X3EFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB RC_OSC EQU 0X3FFF HS_OSC EQU 0X3FFE XT_OSC EQU 0X3FFD LP_OSC EQU 0X3FFC @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & CPD_OFF & DEBUG_ON 16f874: CP_ALL EQU 0X0FCF CP_HALF EQU 0X1FDF CP_UPPER_256 EQU 0X2FEF CP_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF DEBUG_OFF EQU 0X3FFF WRTE_ON EQU 0X3FFF WRTE_OFF EQU 0X3DFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & WRTE_ON & CP_OFF & DEBUG_ON 16f874a: CP_ALL EQU 0X3FFF CP_OFF EQU 0X1FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF WRTE_ON EQU 0X3FFF ; No prog memmory write protection WRTE_256 EQU 0X3DFF ; First 256 prog memmory write protected WRTE_1FOURTH EQU 0X3BFF ; First quarter prog memmory write protected WRTE_HALF EQU 0X39FF ; First half memmory write protected CPD_OFF EQU 0X3FFF CPD_ON EQU 0X3EFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB RC_OSC EQU 0X3FFF HS_OSC EQU 0X3FFE XT_OSC EQU 0X3FFD LP_OSC EQU 0X3FFC @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & CPD_OFF & DEBUG_ON 16f876: CP_ALL EQU 0X0FCF CP_HALF EQU 0X1FDF CP_UPPER_256 EQU 0X2FEF CP_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF DEBUG_OFF EQU 0X3FFF WRTE_ON EQU 0X3FFF WRTE_OFF EQU 0X3DFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & WRTE_ON & CP_OFF & DEBUG_ON 16f876a: CP_ALL EQU 0X3FFF CP_OFF EQU 0X1FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF WRTE_ON EQU 0X3FFF ; No prog memmory write protection WRTE_256 EQU 0X3DFF ; First 256 prog memmory write protected WRTE_1FOURTH EQU 0X3BFF ; First quarter prog memmory write protected WRTE_HALF EQU 0X39FF ; First half memmory write protected CPD_OFF EQU 0X3FFF CPD_ON EQU 0X3EFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB RC_OSC EQU 0X3FFF HS_OSC EQU 0X3FFE XT_OSC EQU 0X3FFD LP_OSC EQU 0X3FFC @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & CPD_OFF & DEBUG_ON 16f877: CP_ALL EQU 0X0FCF CP_HALF EQU 0X1FDF CP_UPPER_256 EQU 0X2FEF CP_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF DEBUG_OFF EQU 0X3FFF WRTE_ON EQU 0X3FFF WRTE_OFF EQU 0X3DFF CPD_ON EQU 0X3EFF CPD_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & WRTE_ON & CP_OFF & DEBUG_ON 16f877a: CP_ALL EQU 0X1FFF CP_OFF EQU 0X3FFF DEBUG_OFF EQU 0X3FFF DEBUG_ON EQU 0X37FF WRT_OFF EQU 0X3FFF ; No prog memmory write protection WRT_256 EQU 0X3DFF ; First 256 prog memory write protected WRT_1FOURTH EQU 0X3BFF ; First quarter prog memmory write protected WRT_HALF EQU 0X39FF ; First half memmory write protected CPD_OFF EQU 0X3FFF CPD_ON EQU 0X3EFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X3F7F BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB RC_OSC EQU 0X3FFF HS_OSC EQU 0X3FFE XT_OSC EQU 0X3FFD LP_OSC EQU 0X3FFC @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BODEN_OFF & LVP_OFF & CP_OFF & CPD_OFF & DEBUG_ON 16f883: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ; Configuration Word1 DEBUG_ON EQU 0X1FFF DEBUG_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X2FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOR_ON EQU 0X3FFF BOR_NSLEEP EQU 0X3EFF BOR_SBODEN EQU 0X3DFF BOR_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_ON EQU 0X3FEF PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF ; Configuration Word2 WRT_OFF EQU 0X3FFF ; No prog memmory write protection WRT_256 EQU 0X3DFF ; First 256 prog memmory write protected WRT_1FOURTH EQU 0X3BFF ; First quarter prog memmory write protected WRT_HALF EQU 0X39FF ; First half memmory write protected BOR21V EQU 0X3EFF BOR40V EQU 0X3FFF @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & DEBUG_ON & FCMEN_OFF & IESO_OFF & BOR_OFF & CPD_OFF & CP_OFF & MCLRE_ON & PWRTE_ON @ __CONFIG _CONFIG2, WRT_OFF & BOR21V 16f884: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ; Configuration Word1 DEBUG_ON EQU 0X1FFF DEBUG_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X2FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOR_ON EQU 0X3FFF BOR_NSLEEP EQU 0X3EFF BOR_SBODEN EQU 0X3DFF BOR_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_ON EQU 0X3FEF PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF ; Configuration Word2 WRT_OFF EQU 0X3FFF ; No prog memmory write protection WRT_256 EQU 0X3DFF ; First 256 prog memmory write protected WRT_1FOURTH EQU 0X3BFF ; First quarter prog memmory write protected WRT_HALF EQU 0X39FF ; First half memmory write protected BOR21V EQU 0X3EFF BOR40V EQU 0X3FFF @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & DEBUG_ON & FCMEN_OFF & IESO_OFF & BOR_OFF & CPD_OFF & CP_OFF & MCLRE_ON & PWRTE_ON @ __CONFIG _CONFIG2, WRT_OFF & BOR21V 16f886: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ; Configuration Word1 DEBUG_ON EQU 0X1FFF DEBUG_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X2FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOR_ON EQU 0X3FFF BOR_NSLEEP EQU 0X3EFF BOR_SBODEN EQU 0X3DFF BOR_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_ON EQU 0X3FEF PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF ; Configuration Word2 WRT_OFF EQU 0X3FFF ; No prog memmory write protection WRT_256 EQU 0X3DFF ; First 256 prog memmory write protected WRT_1FOURTH EQU 0X3BFF ; First quarter prog memmory write protected WRT_HALF EQU 0X39FF ; First half memmory write protected BOR21V EQU 0X3EFF BOR40V EQU 0X3FFF @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & DEBUG_ON & FCMEN_OFF & IESO_OFF & BOR_OFF & CPD_OFF & CP_OFF & MCLRE_ON & PWRTE_ON @ __CONFIG _CONFIG2, WRT_OFF & BOR21V 16f887: _CONFIG1 EQU 0X2007 _CONFIG2 EQU 0X2008 ; Configuration Word1 DEBUG_ON EQU 0X1FFF DEBUG_OFF EQU 0X3FFF LVP_ON EQU 0X3FFF LVP_OFF EQU 0X2FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOR_ON EQU 0X3FFF BOR_NSLEEP EQU 0X3EFF BOR_SBODEN EQU 0X3DFF BOR_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_ON EQU 0X3FEF PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF ; Configuration Word2 WRT_OFF EQU 0X3FFF ; No prog memmory write protection WRT_256 EQU 0X3DFF ; First 256 prog memmory write protected WRT_1FOURTH EQU 0X3BFF ; First quarter prog memmory write protected WRT_HALF EQU 0X39FF ; First half memmory write protected BOR21V EQU 0X3EFF BOR40V EQU 0X3FFF @ CONFIG_REQ @ __CONFIG _CONFIG1, HS_OSC & WDT_ON & DEBUG_ON & FCMEN_OFF & IESO_OFF & BOR_OFF & CPD_OFF & CP_OFF & MCLRE_ON & PWRTE_ON @ __CONFIG _CONFIG2, WRT_OFF & BOR21V 16f913: _CONFIG EQU 0X2007 ;Configuration Byte 1 Options DEBUG_ON EQU 0X2FFF DEBUG_OFF EQU 0X3FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_ON EQU 0X3FEF PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & MCLRE_ON & CP_OFF & CPD_OFF & DEBUG_ON & FCMEN_OFF & IESO_OFF 16f914: _CONFIG EQU 0X2007 DEBUG_ON EQU 0X2FFF DEBUG_OFF EQU 0X3FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_ON EQU 0X3FEF PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & MCLRE_ON & CP_OFF & CPD_OFF & DEBUG_ON & FCMEN_OFF & IESO_OFF 16f916: DEBUG_ON EQU 0X2FFF DEBUG_OFF EQU 0X3FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_ON EQU 0X3FEF PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & MCLRE_ON & CP_OFF & CPD_OFF & DEBUG_ON & FCMEN_OFF & IESO_OFF 16f917: DEBUG_ON EQU 0X2FFF DEBUG_OFF EQU 0X3FFF FCMEN_ON EQU 0X3FFF FCMEN_OFF EQU 0X37FF IESO_ON EQU 0X3FFF IESO_OFF EQU 0X3BFF BOD_ON EQU 0X3FFF BOD_NSLEEP EQU 0X3EFF BOD_SBODEN EQU 0X3DFF BOD_OFF EQU 0X3CFF CPD_ON EQU 0X3F7F CPD_OFF EQU 0X3FFF CP_ON EQU 0X3FBF CP_OFF EQU 0X3FFF MCLRE_ON EQU 0X3FFF MCLRE_OFF EQU 0X3FDF PWRTE_ON EQU 0X3FEF PWRTE_OFF EQU 0X3FFF WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FF7 LP_OSC EQU 0X3FF8 XT_OSC EQU 0X3FF9 HS_OSC EQU 0X3FFA EC_OSC EQU 0X3FFB INTRC_OSC_NOCLKOUT EQU 0X3FFC INTRC_OSC_CLKOUT EQU 0X3FFD EXTRC_OSC_NOCLKOUT EQU 0X3FFE EXTRC_OSC_CLKOUT EQU 0X3FFF INTOSCIO EQU 0X3FFC INTOSC EQU 0X3FFD EXTRCIO EQU 0X3FFE EXTRC EQU 0X3FFF @ CONFIG_REQ @ __config HS_OSC & WDT_ON & PWRTE_ON & BOD_OFF & MCLRE_ON & CP_OFF & CPD_OFF & DEBUG_ON & FCMEN_OFF & IESO_OFF 16x76: BODEN_ON EQU 0X3FFF BODEN_OFF EQU 0X3FBF CP_ALL EQU 0X3FEF CP_OFF EQU 0X3FFF PWRTE_OFF EQU 0X3FFF PWRTE_ON EQU 0X3FF7 WDT_ON EQU 0X3FFF WDT_OFF EQU 0X3FFB LP_OSC EQU 0X3FFC XT_OSC EQU 0X3FFD HS_OSC EQU 0X3FFE RC_OSC EQU 0X3FFF @ CONFIG_REQ @ __config XT_OSC & WDT_ON & PWRTE_ON & BODEN_ON & CP_OFF 18c242: ;Configuration Byte 0 Options CP_ON_0 EQU 0X00 ; Code Protect enable CP_OFF_0 EQU 0XFF ;Configuration Byte 1 Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 3 Options WDT_ON_3 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_3 EQU 0XFE WDTPS_128_3 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_3 EQU 0XFD WDTPS_32_3 EQU 0XFB WDTPS_16_3 EQU 0XF9 WDTPS_8_3 EQU 0XF7 WDTPS_4_3 EQU 0XF5 WDTPS_2_3 EQU 0XF3 WDTPS_1_3 EQU 0XF1 ;Configuration Byte 5 Options CCP2MX_ON_5 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_5 EQU 0XFE ;Configuration Byte 6 Options STVR_ON_6 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_6 EQU 0XFE @ CONFIG_REQ @ __config CONFIG0, CP_OFF_0 @ __config CONFIG1, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2, BOR_ON_2 & BORV_25_2 & PWRT_ON_2 @ __config CONFIG3, WDT_ON_3 & WDTPS_128_3 @ __config CONFIG5, CCP2MX_ON_5 @ __config CONFIG6, STVR_ON_6 18c252: ;Configuration Byte 0 Options CP_ON_0 EQU 0X00 ; Code Protect enable CP_OFF_0 EQU 0XFF ;Configuration Byte 1 Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 3 Options WDT_ON_3 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_3 EQU 0XFE WDTPS_128_3 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_3 EQU 0XFD WDTPS_32_3 EQU 0XFB WDTPS_16_3 EQU 0XF9 WDTPS_8_3 EQU 0XF7 WDTPS_4_3 EQU 0XF5 WDTPS_2_3 EQU 0XF3 WDTPS_1_3 EQU 0XF1 ;Configuration Byte 5 Options CCP2MX_ON_5 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_5 EQU 0XFE ;Configuration Byte 6 Options STVR_ON_6 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_6 EQU 0XFE @ CONFIG_REQ @ __config CONFIG0, CP_OFF_0 @ __config CONFIG1, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2, BOR_ON_2 & BORV_25_2 & PWRT_ON_2 @ __config CONFIG3, WDT_ON_3 & WDTPS_128_3 @ __config CONFIG5, CCP2MX_ON_5 @ __config CONFIG6, STVR_ON_6 18c442: ;Configuration Byte 0 Options CP_ON_0 EQU 0X00 ; Code Protect enable CP_OFF_0 EQU 0XFF ;Configuration Byte 1 Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 3 Options WDT_ON_3 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_3 EQU 0XFE WDTPS_128_3 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_3 EQU 0XFD WDTPS_32_3 EQU 0XFB WDTPS_16_3 EQU 0XF9 WDTPS_8_3 EQU 0XF7 WDTPS_4_3 EQU 0XF5 WDTPS_2_3 EQU 0XF3 WDTPS_1_3 EQU 0XF1 ;Configuration Byte 5 Options CCP2MX_ON_5 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_5 EQU 0XFE ;Configuration Byte 6 Options STVR_ON_6 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_6 EQU 0XFE @ CONFIG_REQ @ __config CONFIG0, CP_OFF_0 @ __config CONFIG1, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2, BOR_ON_2 & BORV_25_2 & PWRT_ON_2 @ __config CONFIG3, WDT_ON_3 & WDTPS_128_3 @ __config CONFIG5, CCP2MX_ON_5 @ __config CONFIG6, STVR_ON_6 18c452: ;Configuration Byte 0 Options CP_ON_0 EQU 0X00 ; Code Protect enable CP_OFF_0 EQU 0XFF ;Configuration Byte 1 Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 3 Options WDT_ON_3 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_3 EQU 0XFE WDTPS_128_3 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_3 EQU 0XFD WDTPS_32_3 EQU 0XFB WDTPS_16_3 EQU 0XF9 WDTPS_8_3 EQU 0XF7 WDTPS_4_3 EQU 0XF5 WDTPS_2_3 EQU 0XF3 WDTPS_1_3 EQU 0XF1 ;Configuration Byte 5 Options CCP2MX_ON_5 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_5 EQU 0XFE ;Configuration Byte 6 Options STVR_ON_6 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_6 EQU 0XFE @ CONFIG_REQ @ __config CONFIG0, CP_OFF_0 @ __config CONFIG1, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2, BOR_ON_2 & BORV_25_2 & PWRT_ON_2 @ __config CONFIG3, WDT_ON_3 & WDTPS_128_3 @ __config CONFIG5, CCP2MX_ON_5 @ __config CONFIG6, STVR_ON_6 18c658: ;Configuration Byte 0 Options CP_ON_0 EQU 0X00 ; Code Protect enable CP_OFF_0 EQU 0XFF ;Configuration Byte 1 Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 3 Options WDT_ON_3 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_3 EQU 0XFE WDTPS_128_3 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_3 EQU 0XFD WDTPS_32_3 EQU 0XFB WDTPS_16_3 EQU 0XF9 WDTPS_8_3 EQU 0XF7 WDTPS_4_3 EQU 0XF5 WDTPS_2_3 EQU 0XF3 WDTPS_1_3 EQU 0XF1 ;Configuration Byte 6 Options STVR_ON_6 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_6 EQU 0XFE @ CONFIG_REQ @ __config CONFIG0, CP_OFF_0 @ __config CONFIG1, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2, BOR_ON_2 & BORV_25_2 & PWRT_ON_2 @ __config CONFIG3, WDT_ON_3 & WDTPS_128_3 @ __config CONFIG6, STVR_ON_6 18c858: ;Configuration Byte 0 Options CP_ON_0 EQU 0X00 ; Code Protect enable CP_OFF_0 EQU 0XFF ;Configuration Byte 1 Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 3 Options WDT_ON_3 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_3 EQU 0XFE WDTPS_128_3 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_3 EQU 0XFD WDTPS_32_3 EQU 0XFB WDTPS_16_3 EQU 0XF9 WDTPS_8_3 EQU 0XF7 WDTPS_4_3 EQU 0XF5 WDTPS_2_3 EQU 0XF3 WDTPS_1_3 EQU 0XF1 ;Configuration Byte 6 Options STVR_ON_6 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_6 EQU 0XFE @ CONFIG_REQ @ __config CONFIG0, CP_OFF_0 @ __config CONFIG1, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2, BOR_ON_2 & BORV_25_2 & PWRT_ON_2 @ __config CONFIG3, WDT_ON_3 & WDTPS_128_3 @ __config CONFIG6, STVR_ON_6 18f242: ;Configuration Byte 1H Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_2 EQU 0XFE WDTPS_128_2 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_2 EQU 0XFD WDTPS_32_2 EQU 0XFB WDTPS_16_2 EQU 0XF9 WDTPS_8_2 EQU 0XF7 WDTPS_4_2 EQU 0XF5 WDTPS_2_2 EQU 0XF3 WDTPS_1_2 EQU 0XF1 ;Configuration Byte 3H Options CCP2MX_ON_3 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_3 EQU 0XFE ;Configuration Byte 4L Options STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_4 EQU 0XFE LVP_ON_4 EQU 0XFF ; Low-voltage ICSP enable LVP_OFF_4 EQU 0XFB DEBUG_ON_4 EQU 0X7F ; Backgound Debugger enable DEBUG_OFF_4 EQU 0XFF ;Configuration Byte 5L Options CP0_ON_5 EQU 0XFE ; Code protect user block enable CP0_OFF_5 EQU 0XFF CP1_ON_5 EQU 0XFD CP1_OFF_5 EQU 0XFF CP2_ON_5 EQU 0XFB CP2_OFF_5 EQU 0XFF CP3_ON_5 EQU 0XF7 CP3_OFF_5 EQU 0XFF ;Configuration Byte 5H Options CPB_ON_5 EQU 0XBF ; Code protect boot block enable CPB_OFF_5 EQU 0XFF CPD_ON_5 EQU 0X7F ; Code protect Data EE enable CPD_OFF_5 EQU 0XFF ;Configuration Byte 6L Options WRT0_ON_6 EQU 0XFE ; Write protect user block enable WRT0_OFF_6 EQU 0XFF WRT1_ON_6 EQU 0XFD WRT1_OFF_6 EQU 0XFF WRT2_ON_6 EQU 0XFB WRT2_OFF_6 EQU 0XFF WRT3_ON_6 EQU 0XF7 WRT3_OFF_6 EQU 0XFF ;Configuration Byte 6H Options WRTC_ON_6 EQU 0XDF ; Write protect CONFIG regs enable WRTC_OFF_6 EQU 0XFF WRTB_ON_6 EQU 0XBF ; Write protect boot block enable WRTB_OFF_6 EQU 0XFF WRTD_ON_6 EQU 0X7F ; Write protect Data EE enable WRTD_OFF_6 EQU 0XFF ;Configuration Byte 7L Options EBTR0_ON_7 EQU 0XFE ; Table Read protect user block enable EBTR0_OFF_7 EQU 0XFF EBTR1_ON_7 EQU 0XFD EBTR1_OFF_7 EQU 0XFF EBTR2_ON_7 EQU 0XFB EBTR2_OFF_7 EQU 0XFF EBTR3_ON_7 EQU 0XF7 EBTR3_OFF_7 EQU 0XFF ;Configuration Byte 7H Options EBTRB_ON_7 EQU 0XBF ; Table Read protect boot block enable EBTRB_OFF_7 EQU 0XFF @ CONFIG_REQ @ __config CONFIG1H, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, CCP2MX_ON_3 @ __config CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f248: ;Configuration Byte 1L Options CP_ON_1L EQU 0X00 ; Code Protect enable CP_OFF_1L EQU 0XFF ;Configuration Byte 1H Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_2 EQU 0XFE WDTPS_128_2 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_2 EQU 0XFD WDTPS_32_2 EQU 0XFB WDTPS_16_2 EQU 0XF9 WDTPS_8_2 EQU 0XF7 WDTPS_4_2 EQU 0XF5 WDTPS_2_2 EQU 0XF3 WDTPS_1_2 EQU 0XF1 ;Configuration Byte 4L Options STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_4 EQU 0XFE @ CONFIG_REQ @ __config CONFIG1H, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG4L, STVR_ON_4 18f252: ;Configuration Byte 1H Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_2 EQU 0XFE WDTPS_128_2 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_2 EQU 0XFD WDTPS_32_2 EQU 0XFB WDTPS_16_2 EQU 0XF9 WDTPS_8_2 EQU 0XF7 WDTPS_4_2 EQU 0XF5 WDTPS_2_2 EQU 0XF3 WDTPS_1_2 EQU 0XF1 ;Configuration Byte 3H Options CCP2MX_ON_3 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_3 EQU 0XFE ;Configuration Byte 4L Options STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_4 EQU 0XFE LVP_ON_4 EQU 0XFF ; Low-voltage ICSP enable LVP_OFF_4 EQU 0XFB DEBUG_ON_4 EQU 0X7F ; Backgound Debugger enable DEBUG_OFF_4 EQU 0XFF ;Configuration Byte 5L Options CP0_ON_5 EQU 0XFE ; Code protect user block enable CP0_OFF_5 EQU 0XFF CP1_ON_5 EQU 0XFD CP1_OFF_5 EQU 0XFF CP2_ON_5 EQU 0XFB CP2_OFF_5 EQU 0XFF CP3_ON_5 EQU 0XF7 CP3_OFF_5 EQU 0XFF ;Configuration Byte 5H Options CPB_ON_5 EQU 0XBF ; Code protect boot block enable CPB_OFF_5 EQU 0XFF CPD_ON_5 EQU 0X7F ; Code protect Data EE enable CPD_OFF_5 EQU 0XFF ;Configuration Byte 6L Options WRT0_ON_6 EQU 0XFE ; Write protect user block enable WRT0_OFF_6 EQU 0XFF WRT1_ON_6 EQU 0XFD WRT1_OFF_6 EQU 0XFF WRT2_ON_6 EQU 0XFB WRT2_OFF_6 EQU 0XFF WRT3_ON_6 EQU 0XF7 WRT3_OFF_6 EQU 0XFF ;Configuration Byte 6H Options WRTC_ON_6 EQU 0XDF ; Write protect CONFIG regs enable WRTC_OFF_6 EQU 0XFF WRTB_ON_6 EQU 0XBF ; Write protect boot block enable WRTB_OFF_6 EQU 0XFF WRTD_ON_6 EQU 0X7F ; Write protect Data EE enable WRTD_OFF_6 EQU 0XFF ;Configuration Byte 7L Options EBTR0_ON_7 EQU 0XFE ; Table Read protect user block enable EBTR0_OFF_7 EQU 0XFF EBTR1_ON_7 EQU 0XFD EBTR1_OFF_7 EQU 0XFF EBTR2_ON_7 EQU 0XFB EBTR2_OFF_7 EQU 0XFF EBTR3_ON_7 EQU 0XF7 EBTR3_OFF_7 EQU 0XFF ;Configuration Byte 7H Options EBTRB_ON_7 EQU 0XBF ; Table Read protect boot block enable EBTRB_OFF_7 EQU 0XFF @ CONFIG_REQ @ __config CONFIG1H, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, CCP2MX_ON_3 @ __config CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f258: ;Configuration Byte 1L Options CP_ON_1L EQU 0X00 ; Code Protect enable CP_OFF_1L EQU 0XFF ;Configuration Byte 1H Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_2 EQU 0XFE WDTPS_128_2 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_2 EQU 0XFD WDTPS_32_2 EQU 0XFB WDTPS_16_2 EQU 0XF9 WDTPS_8_2 EQU 0XF7 WDTPS_4_2 EQU 0XF5 WDTPS_2_2 EQU 0XF3 WDTPS_1_2 EQU 0XF1 ;Configuration Byte 4L Options STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_4 EQU 0XFE @ CONFIG_REQ @ __config CONFIG1H, OSCS_OFF_1 & HS_OSC_1 @ __config CONFIG2L, BOR_ON_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG4L, STVR_ON_4 18f442: OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_2 EQU 0XFE WDTPS_128_2 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_2 EQU 0XFD WDTPS_32_2 EQU 0XFB WDTPS_16_2 EQU 0XF9 WDTPS_8_2 EQU 0XF7 WDTPS_4_2 EQU 0XF5 WDTPS_2_2 EQU 0XF3 WDTPS_1_2 EQU 0XF1 ;Configuration Byte 3H Options CCP2MX_ON_3 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_3 EQU 0XFE ;Configuration Byte 4L Options STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_4 EQU 0XFE LVP_ON_4 EQU 0XFF ; Low-voltage ICSP enable LVP_OFF_4 EQU 0XFB DEBUG_ON_4 EQU 0X7F ; Backgound Debugger enable DEBUG_OFF_4 EQU 0XFF ;Configuration Byte 5L Options CP0_ON_5 EQU 0XFE ; Code protect user block enable CP0_OFF_5 EQU 0XFF CP1_ON_5 EQU 0XFD CP1_OFF_5 EQU 0XFF CP2_ON_5 EQU 0XFB CP2_OFF_5 EQU 0XFF CP3_ON_5 EQU 0XF7 CP3_OFF_5 EQU 0XFF ;Configuration Byte 5H Options CPB_ON_5 EQU 0XBF ; Code protect boot block enable CPB_OFF_5 EQU 0XFF CPD_ON_5 EQU 0X7F ; Code protect Data EE enable CPD_OFF_5 EQU 0XFF ;Configuration Byte 6L Options WRT0_ON_6 EQU 0XFE ; Write protect user block enable WRT0_OFF_6 EQU 0XFF WRT1_ON_6 EQU 0XFD WRT1_OFF_6 EQU 0XFF WRT2_ON_6 EQU 0XFB WRT2_OFF_6 EQU 0XFF WRT3_ON_6 EQU 0XF7 WRT3_OFF_6 EQU 0XFF ;Configuration Byte 6H Options WRTC_ON_6 EQU 0XDF ; Write protect CONFIG regs enable WRTC_OFF_6 EQU 0XFF WRTB_ON_6 EQU 0XBF ; Write protect boot block enable WRTB_OFF_6 EQU 0XFF WRTD_ON_6 EQU 0X7F ; Write protect Data EE enable WRTD_OFF_6 EQU 0XFF ;Configuration Byte 7L Options EBTR0_ON_7 EQU 0XFE ; Table Read protect user block enable EBTR0_OFF_7 EQU 0XFF EBTR1_ON_7 EQU 0XFD EBTR1_OFF_7 EQU 0XFF EBTR2_ON_7 EQU 0XFB EBTR2_OFF_7 EQU 0XFF EBTR3_ON_7 EQU 0XF7 EBTR3_OFF_7 EQU 0XFF ;Configuration Byte 7H Options EBTRB_ON_7 EQU 0XBF ; Table Read protect boot block enable EBTRB_OFF_7 EQU 0XFF @ CONFIG_REQ @ __config CONFIG1H, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, CCP2MX_ON_3 @ __config CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f448: ;Configuration Byte 1L Options CP_ON_1L EQU 0X00 ; Code Protect enable CP_OFF_1L EQU 0XFF ;Configuration Byte 1H Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_25_2 EQU 0XFF ; BOR Voltage - 2.5v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_2 EQU 0XFE WDTPS_128_2 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_2 EQU 0XFD WDTPS_32_2 EQU 0XFB WDTPS_16_2 EQU 0XF9 WDTPS_8_2 EQU 0XF7 WDTPS_4_2 EQU 0XF5 WDTPS_2_2 EQU 0XF3 WDTPS_1_2 EQU 0XF1 ;Configuration Byte 4L Options STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_4 EQU 0XFE @ CONFIG_REQ @ __config CONFIG1H, OSCS_OFF_1 & HS_OSC_1 @ __config CONFIG2L, BOR_ON_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG4L, STVR_ON_4 18f4585: OSC_LP_1 EQU 0XF0 ; LP OSC_XT_1 EQU 0XF1 ; XT OSC_HS_1 EQU 0XF2 ; HS OSC_RC_1 EQU 0XF3 ; External RC with OSC2 as divide by 4 clock out OSC_EC_1 EQU 0XF4 ; EC with OSC2 as divide by 4 clock out OSC_ECIO_1 EQU 0XF5 ; EC with OSC2 as RA6 OSC_HSPLL_1 EQU 0XF6 ; HS with HW enabled 4xPLL OSC_RCIO_1 EQU 0XF7 ; External RC with OSC2 as RA6 OSC_IRCIO67_1 EQU 0XF8 ; Internal RC with OSC2 as RA6 and OSC1 as RA7 OSC_IRCIO7_1 EQU 0XF9 ; Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out OSC_ERC1_1 EQU 0XFA ; External RC with OSC2 as divide by 4 clock out OSC_ERC_1 EQU 0XFC ; External RC with OSC2 as divide by 4 clock out FCMENB_OFF_1 EQU 0XBF ; Disabled FCMENB_ON_1 EQU 0XFF ; Enabled IESOB_OFF_1 EQU 0X7F ; Disabled IESOB_ON_1 EQU 0XFF ; Enabled ; CONFIG2L Options PWRT_ON_2 EQU 0XFE ; Enabled PWRT_OFF_2 EQU 0XFF ; Disabled BOR_OFF_2 EQU 0XF9 ; Disabled BOR_SBORENCTRL_2 EQU 0XFB ; Controlled by SBOREN BOR_BOACTIVE_2 EQU 0XFD ; Enabled whenever Part is Active - SBOREN Disabled BOR_BOHW_2 EQU 0XFF ; Enabled in HW, SBOREN disabled BORV_45_2 EQU 0XE7 ; 4.5V BORV_42_2 EQU 0XEF ; 4.2V BORV_27_2 EQU 0XF7 ; 2.7V BORV_20_2 EQU 0XFF ; 2.0V ; CONFIG2H Options WDT_OFF_2 EQU 0XFE ; HW Disabled - SW Controlled WDT_ON_2 EQU 0XFF ; HW Enabled - SW Disabled WDTPS_1_2 EQU 0XE1 ; 1:1 WDTPS_2_2 EQU 0XE3 ; 1:2 WDTPS_4_2 EQU 0XE5 ; 1:4 WDTPS_8_2 EQU 0XE7 ; 1:8 WDTPS_16_2 EQU 0XE9 ; 1:16 WDTPS_32_2 EQU 0XEB ; 1:32 WDTPS_64_2 EQU 0XED ; 1:64 WDTPS_128_2 EQU 0XEF ; 1:128 WDTPS_256_2 EQU 0XF1 ; 1:256 WDTPS_512_2 EQU 0XF3 ; 1:512 WDTPS_1024_2 EQU 0XF5 ; 1:1024 WDTPS_2048_2 EQU 0XF7 ; 1:2048 WDTPS_4096_2 EQU 0XF9 ; 1:4096 WDTPS_8192_2 EQU 0XFB ; 1:8192 WDTPS_16384_2 EQU 0XFD ; 1:16384 WDTPS_32768_2 EQU 0XFF ; 1:32768 ; CONFIG3H Options MCLRE_OFF_3 EQU 0X7F ; Disabled MCLRE_ON_3 EQU 0XFF ; Enabled LPT1OSC_OFF_3 EQU 0XFB ; Timer1 Low Power Oscillator disabled LPT1OSC_ON_3 EQU 0XFF ; Timer1 Low Power Oscillator Active PBADEN_OFF_3 EQU 0XFD ; Port B<4> and Port B<1:0> Configured as Digital I/O Pins on Reset PBADEN_ON_3 EQU 0XFF ; Port B<4> and Port B<1:0> Configured as Analog Pins on Reset ; CONFIG4L Options DEBUG_ON_4 EQU 0X7F ; Enabled DEBUG_OFF_4 EQU 0XFF ; Disabled XINST_OFF_4 EQU 0XBF ; Disabled XINST_ON_4 EQU 0XFF ; Enabled BBSIZ_1Kword_4 EQU 0XCF ; 1Kwords (2kbytes) Boot Block BBSIZ_2Kwords_4 EQU 0XDF ; 2Kwords (4kbytes) Boot Block BBSIZ_4Kwords_4 EQU 0XEF ; 4Kwords (8kbytes) Boot Block LVP_OFF_4 EQU 0XFB ; Disabled LVP_ON_4 EQU 0XFF ; Enabled STVREN_OFF_4 EQU 0XFE ; Disabled STVREN_ON_4 EQU 0XFF ; Enabled ; CONFIG5L Options CP0_ON_5 EQU 0XFE ; Enabled CP0_OFF_5 EQU 0XFF ; Disabled CP1_ON_5 EQU 0XFD ; Enabled CP1_OFF_5 EQU 0XFF ; Disabled CP2_ON_5 EQU 0XFB ; Enabled CP2_OFF_5 EQU 0XFF ; Disabled CP3_ON_5 EQU 0XF7 ; Enabled CP3_OFF_5 EQU 0XFF ; Disabled ; CONFIG5H Options CPB_ON_5 EQU 0XBF ; Enabled CPB_OFF_5 EQU 0XFF ; Disabled CPD_ON_5 EQU 0X7F ; Enabled CPD_OFF_5 EQU 0XFF ; Disabled ; CONFIG6L Options WRT0_ON_6 EQU 0XFE ; Enabled WRT0_OFF_6 EQU 0XFF ; Disabled WRT1_ON_6 EQU 0XFD ; Enabled WRT1_OFF_6 EQU 0XFF ; Disabled WRT2_ON_6 EQU 0XFB ; Enabled WRT2_OFF_6 EQU 0XFF ; Disabled WRT3_ON_6 EQU 0XF7 ; Enabled WRT3_OFF_6 EQU 0XFF ; Disabled ; CONFIG6H Options WRTB_ON_6 EQU 0XBF ; Enabled WRTB_OFF_6 EQU 0XFF ; Disabled WRTC_ON_6 EQU 0XDF ; Enabled WRTC_OFF_6 EQU 0XFF ; Disabled WRTD_ON_6 EQU 0X7F ; Enabled WRTD_OFF_6 EQU 0XFF ; Disabled ; CONFIG7L Options EBTR0_ON_7 EQU 0XFE ; Enabled EBTR0_OFF_7 EQU 0XFF ; Disabled EBTR1_ON_7 EQU 0XFD ; Enabled EBTR1_OFF_7 EQU 0XFF ; Disabled EBTR2_ON_7 EQU 0XFB ; Enabled EBTR2_OFF_7 EQU 0XFF ; Disabled EBTR3_ON_7 EQU 0XF7 ; Enabled EBTR3_OFF_7 EQU 0XFF ; Disabled ; CONFIG7H Options EBTRB_ON_7 EQU 0XBF ; Enabled EBTRB_OFF_7 EQU 0XFF ; Disabled @ CONFIG_REQ @ __config CONFIG1H, OSC_HS_1 @ __config CONFIG2L, BORV_27_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, PBADEN_OFF_3 @__config CONFIG4L, STVREN_ON_4 & LVP_OFF_4 & DEBUG_ON_4 & XINST_OFF_4 & BBSIZ_1Kword_4 18f4580: ; CONFIG1H Options OSC_LP_1 EQU 0XF0 ; LP OSC_XT_1 EQU 0XF1 ; XT OSC_HS_1 EQU 0XF2 ; HS OSC_RC_1 EQU 0XF3 ; External RC with OSC2 as divide by 4 clock out OSC_EC_1 EQU 0XF4 ; EC with OSC2 as divide by 4 clock out OSC_ECIO_1 EQU 0XF5 ; EC with OSC2 as RA6 OSC_HSPLL_1 EQU 0XF6 ; HS with HW enabled 4xPLL OSC_RCIO_1 EQU 0XF7 ; External RC with OSC2 as RA6 OSC_IRCIO67_1 EQU 0XF8 ; Internal RC with OSC2 as RA6 and OSC1 as RA7 OSC_IRCIO7_1 EQU 0XF9 ; Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out OSC_ERC1_1 EQU 0XFA ; External RC with OSC2 as divide by 4 clock out OSC_ERC_1 EQU 0XFC ; External RC with OSC2 as divide by 4 clock out FCMENB_OFF_1 EQU 0XBF ; Disabled FCMENB_ON_1 EQU 0XFF ; Enabled IESOB_OFF_1 EQU 0X7F ; Disabled IESOB_ON_1 EQU 0XFF ; Enabled ; CONFIG2L Options PWRT_ON_2 EQU 0XFE ; Enabled PWRT_OFF_2 EQU 0XFF ; Disabled BOR_OFF_2 EQU 0XF9 ; Disabled BOR_SBORENCTRL_2 EQU 0XFB ; Controlled by SBOREN BOR_BOACTIVE_2 EQU 0XFD ; Enabled whenever Part is Active - SBOREN Disabled BOR_BOHW_2 EQU 0XFF ; Enabled in HW, SBOREN disabled BORV_45_2 EQU 0XE7 ; 4.5V BORV_42_2 EQU 0XEF ; 4.2V BORV_27_2 EQU 0XF7 ; 2.7V BORV_20_2 EQU 0XFF ; 2.0V ; CONFIG2H Options WDT_OFF_2 EQU 0XFE ; HW Disabled - SW Controlled WDT_ON_2 EQU 0XFF ; HW Enabled - SW Disabled WDTPS_1_2 EQU 0XE1 ; 1:1 WDTPS_2_2 EQU 0XE3 ; 1:2 WDTPS_4_2 EQU 0XE5 ; 1:4 WDTPS_8_2 EQU 0XE7 ; 1:8 WDTPS_16_2 EQU 0XE9 ; 1:16 WDTPS_32_2 EQU 0XEB ; 1:32 WDTPS_64_2 EQU 0XED ; 1:64 WDTPS_128_2 EQU 0XEF ; 1:128 WDTPS_256_2 EQU 0XF1 ; 1:256 WDTPS_512_2 EQU 0XF3 ; 1:512 WDTPS_1024_2 EQU 0XF5 ; 1:1024 WDTPS_2048_2 EQU 0XF7 ; 1:2048 WDTPS_4096_2 EQU 0XF9 ; 1:4096 WDTPS_8192_2 EQU 0XFB ; 1:8192 WDTPS_16384_2 EQU 0XFD ; 1:16384 WDTPS_32768_2 EQU 0XFF ; 1:32768 ; CONFIG3H Options MCLRE_OFF_3 EQU 0X7F ; Disabled MCLRE_ON_3 EQU 0XFF ; Enabled LPT1OSC_OFF_3 EQU 0XFB ; Timer1 Low Power Oscillator disabled LPT1OSC_ON_3 EQU 0XFF ; Timer1 Low Power Oscillator Active PBADEN_OFF_3 EQU 0XFD ; Port B<4> and Port B<1:0> Configured as Digital I/O Pins on Reset PBADEN_ON_3 EQU 0XFF ; Port B<4> and Port B<1:0> Configured as Analog Pins on Reset ; CONFIG4L Options DEBUG_ON_4 EQU 0X7F ; Enabled DEBUG_OFF_4 EQU 0XFF ; Disabled XINST_OFF_4 EQU 0XBF ; Disabled XINST_ON_4 EQU 0XFF ; Enabled BBSIZ_1024_4 EQU 0XEF ; 1K words (2K bytes) Boot Block BBSIZ_2048_4 EQU 0XFF ; 2K words (4K bytes) Boot Block LVP_OFF_4 EQU 0XFB ; Disabled LVP_ON_4 EQU 0XFF ; Enabled STVREN_OFF_4 EQU 0XFE ; Disabled STVREN_ON_4 EQU 0XFF ; Enabled ; CONFIG5L Options CP0_ON_5 EQU 0XFE ; Enabled CP0_OFF_5 EQU 0XFF ; Disabled CP1_ON_5 EQU 0XFD ; Enabled CP1_OFF_5 EQU 0XFF ; Disabled CP2_ON_5 EQU 0XFB ; Enabled CP2_OFF_5 EQU 0XFF ; Disabled CP3_ON_5 EQU 0XF7 ; Enabled CP3_OFF_5 EQU 0XFF ; Disabled ; CONFIG5H Options CPB_ON_5 EQU 0XBF ; Enabled CPB_OFF_5 EQU 0XFF ; Disabled CPD_ON_5 EQU 0X7F ; Enabled CPD_OFF_5 EQU 0XFF ; Disabled ; CONFIG6L Options WRT0_ON_6 EQU 0XFE ; Enabled WRT0_OFF_6 EQU 0XFF ; Disabled WRT1_ON_6 EQU 0XFD ; Enabled WRT1_OFF_6 EQU 0XFF ; Disabled WRT2_ON_6 EQU 0XFB ; Enabled WRT2_OFF_6 EQU 0XFF ; Disabled WRT3_ON_6 EQU 0XF7 ; Enabled WRT3_OFF_6 EQU 0XFF ; Disabled ; CONFIG6H Options WRTB_ON_6 EQU 0XBF ; Enabled WRTB_OFF_6 EQU 0XFF ; Disabled WRTC_ON_6 EQU 0XDF ; Enabled WRTC_OFF_6 EQU 0XFF ; Disabled WRTD_ON_6 EQU 0X7F ; Enabled WRTD_OFF_6 EQU 0XFF ; Disabled ; CONFIG7L Options EBTR0_ON_7 EQU 0XFE ; Enabled EBTR0_OFF_7 EQU 0XFF ; Disabled EBTR1_ON_7 EQU 0XFD ; Enabled EBTR1_OFF_7 EQU 0XFF ; Disabled EBTR2_ON_7 EQU 0XFB ; Enabled EBTR2_OFF_7 EQU 0XFF ; Disabled EBTR3_ON_7 EQU 0XF7 ; Enabled EBTR3_OFF_7 EQU 0XFF ; Disabled ; CONFIG7H Options EBTRB_ON_7 EQU 0XBF ; Enabled EBTRB_OFF_7 EQU 0XFF ; Disabled @ CONFIG_REQ @ __config CONFIG1H, OSC_HSPLL_1 @ __config CONFIG2L, BORV_27_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, PBADEN_OFF_3 @ __config CONFIG4L, STVREN_ON_4 & LVP_OFF_4 & DEBUG_ON_4 & XINST_OFF_4 & BBSIZ_1024_4 18f452: ;Configuration Byte 1H Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_2 EQU 0XFE WDTPS_128_2 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_2 EQU 0XFD WDTPS_32_2 EQU 0XFB WDTPS_16_2 EQU 0XF9 WDTPS_8_2 EQU 0XF7 WDTPS_4_2 EQU 0XF5 WDTPS_2_2 EQU 0XF3 WDTPS_1_2 EQU 0XF1 ;Configuration Byte 3H Options CCP2MX_ON_3 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_3 EQU 0XFE ;Configuration Byte 4L Options STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_4 EQU 0XFE LVP_ON_4 EQU 0XFF ; Low-voltage ICSP enable LVP_OFF_4 EQU 0XFB DEBUG_ON_4 EQU 0X7F ; Backgound Debugger enable DEBUG_OFF_4 EQU 0XFF ;Configuration Byte 5L Options CP0_ON_5 EQU 0XFE ; Code protect user block enable CP0_OFF_5 EQU 0XFF CP1_ON_5 EQU 0XFD CP1_OFF_5 EQU 0XFF CP2_ON_5 EQU 0XFB CP2_OFF_5 EQU 0XFF CP3_ON_5 EQU 0XF7 CP3_OFF_5 EQU 0XFF ;Configuration Byte 5H Options CPB_ON_5 EQU 0XBF ; Code protect boot block enable CPB_OFF_5 EQU 0XFF CPD_ON_5 EQU 0X7F ; Code protect Data EE enable CPD_OFF_5 EQU 0XFF ;Configuration Byte 6L Options WRT0_ON_6 EQU 0XFE ; Write protect user block enable WRT0_OFF_6 EQU 0XFF WRT1_ON_6 EQU 0XFD WRT1_OFF_6 EQU 0XFF WRT2_ON_6 EQU 0XFB WRT2_OFF_6 EQU 0XFF WRT3_ON_6 EQU 0XF7 WRT3_OFF_6 EQU 0XFF ;Configuration Byte 6H Options WRTC_ON_6 EQU 0XDF ; Write protect CONFIG regs enable WRTC_OFF_6 EQU 0XFF WRTB_ON_6 EQU 0XBF ; Write protect boot block enable WRTB_OFF_6 EQU 0XFF WRTD_ON_6 EQU 0X7F ; Write protect Data EE enable WRTD_OFF_6 EQU 0XFF ;Configuration Byte 7L Options EBTR0_ON_7 EQU 0XFE ; Table Read protect user block enable EBTR0_OFF_7 EQU 0XFF EBTR1_ON_7 EQU 0XFD EBTR1_OFF_7 EQU 0XFF EBTR2_ON_7 EQU 0XFB EBTR2_OFF_7 EQU 0XFF EBTR3_ON_7 EQU 0XF7 EBTR3_OFF_7 EQU 0XFF ;Configuration Byte 7H Options EBTRB_ON_7 EQU 0XBF ; Table Read protect boot block enable EBTRB_OFF_7 EQU 0XFF @ CONFIG_REQ @ __config CONFIG1H, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, CCP2MX_ON_3 @ __config CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f458: ;Configuration Byte 1L Options CP_ON_1L EQU 0X00 ; Code Protect enable CP_OFF_1L EQU 0XFF ;Configuration Byte 1H Options OSCS_ON_1 EQU 0XDF ; Oscillator Switch enable OSCS_OFF_1 EQU 0XFF LP_OSC_1 EQU 0XF8 ; Oscillator type XT_OSC_1 EQU 0XF9 HS_OSC_1 EQU 0XFA RC_OSC_1 EQU 0XFB EC_OSC_1 EQU 0XFC ; External Clock w/OSC2 output divide by 4 ECIO_OSC_1 EQU 0XFD ; w/OSC2 as an IO pin (RA6) HSPLL_OSC_1 EQU 0XFE ; HS PLL RCIO_OSC_1 EQU 0XFF ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options BOR_ON_2 EQU 0XFF ; Brown-Out Reset enable BOR_OFF_2 EQU 0XFD PWRT_OFF_2 EQU 0XFF ; Power-Up Timer enable PWRT_ON_2 EQU 0XFE BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enable WDT_OFF_2 EQU 0XFE WDTPS_128_2 EQU 0XFF ; Watch Dog Timer PostScaler count WDTPS_64_2 EQU 0XFD WDTPS_32_2 EQU 0XFB WDTPS_16_2 EQU 0XF9 WDTPS_8_2 EQU 0XF7 WDTPS_4_2 EQU 0XF5 WDTPS_2_2 EQU 0XF3 WDTPS_1_2 EQU 0XF1 ;Configuration Byte 3H Options CCP2MX_ON_3 EQU 0XFF ; CCP2 pin Mux enable CCP2MX_OFF_3 EQU 0XFE ;Configuration Byte 4L Options STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enable STVR_OFF_4 EQU 0XFE LVP_ON_4 EQU 0XFF ; Low-voltage ICSP enable LVP_OFF_4 EQU 0XFB DEBUG_ON_4 EQU 0X7F ; Backgound Debugger enable DEBUG_OFF_4 EQU 0XFF ;Configuration Byte 5L Options CP0_ON_5 EQU 0XFE ; Code protect user block enable CP0_OFF_5 EQU 0XFF CP1_ON_5 EQU 0XFD CP1_OFF_5 EQU 0XFF CP2_ON_5 EQU 0XFB CP2_OFF_5 EQU 0XFF CP3_ON_5 EQU 0XF7 CP3_OFF_5 EQU 0XFF ;Configuration Byte 5H Options CPB_ON_5 EQU 0XBF ; Code protect boot block enable CPB_OFF_5 EQU 0XFF CPD_ON_5 EQU 0X7F ; Code protect Data EE enable CPD_OFF_5 EQU 0XFF ;Configuration Byte 6L Options WRT0_ON_6 EQU 0XFE ; Write protect user block enable WRT0_OFF_6 EQU 0XFF WRT1_ON_6 EQU 0XFD WRT1_OFF_6 EQU 0XFF WRT2_ON_6 EQU 0XFB WRT2_OFF_6 EQU 0XFF WRT3_ON_6 EQU 0XF7 WRT3_OFF_6 EQU 0XFF ;Configuration Byte 6H Options WRTC_ON_6 EQU 0XDF ; Write protect CONFIG regs enable WRTC_OFF_6 EQU 0XFF WRTB_ON_6 EQU 0XBF ; Write protect boot block enable WRTB_OFF_6 EQU 0XFF WRTD_ON_6 EQU 0X7F ; Write protect Data EE enable WRTD_OFF_6 EQU 0XFF ;Configuration Byte 7L Options EBTR0_ON_7 EQU 0XFE ; Table Read protect user block enable EBTR0_OFF_7 EQU 0XFF EBTR1_ON_7 EQU 0XFD EBTR1_OFF_7 EQU 0XFF EBTR2_ON_7 EQU 0XFB EBTR2_OFF_7 EQU 0XFF EBTR3_ON_7 EQU 0XF7 EBTR3_OFF_7 EQU 0XFF ;Configuration Byte 7H Options EBTRB_ON_7 EQU 0XBF ; Table Read protect boot block enable EBTRB_OFF_7 EQU 0XFF @ CONFIG_REQ @ __config CONFIG1H, OSCS_OFF_1 & HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_OFF_2 & WDTPS_128_2 @ __config CONFIG4L, STVR_ON_4 18f1220: ;Configuration Byte 1H Options IESO_ON_1 EQU 0XFF ; Internal External Oscillator Switch Over mode enabled IESO_OFF_1 EQU 0X7F ; Internal External Oscillator Switch Over mode disabled FSCMEN_ON_1 EQU 0XFF ; Fail Safe Clock Monitor enabled FSCMEN_OFF_1 EQU 0XBF ; Fail Safe Clock Monitor disabled RC_OSC_1 EQU 0XFF ; External RC on OSC1, OSC2 as Fosc/4 RCIO6_OSC_1 EQU 0XF7 ; External RC on OSC1, OSC2 as RA6 LP_OSC_1 EQU 0XF0 ; LP Oscillator XT_OSC_1 EQU 0XF1 ; XT Oscillator HS_OSC_1 EQU 0XF2 ; HS Oscillator HSPLL_OSC_1 EQU 0XF6 ; HS + PLL EC_OSC_1 EQU 0XF4 ; External Clock on OSC1, OSC2 as Fosc/4 ECIO6_OSC_1 EQU 0XF5 ; External Clock on OSC1, OSC2 as RA6 INTIO7_OSC_1 EQU 0XF9 ; Internal RC, OSC1 as RA7, OSC2 as Fosc/4 INTIO67_OSC_1 EQU 0XF8 ; Internal RC, OSC1 as RA7, OSC2 as RA6 ;Configuration Byte 2L Options BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v BOR_ON_2 EQU 0XFF ; Brown-Out Reset enabled BOR_OFF_2 EQU 0XFD ; Brown-Out Reset disabled PWRT_OFF_2 EQU 0XFF ; Power-Up Timer disabled PWRT_ON_2 EQU 0XFE ; Power-Up Timer enabled ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enabled WDT_OFF_2 EQU 0XFE ; Watch Dog Timer disabled WDTPS_32K_2 EQU 0XFF ; 1:32,768 WDT Postscaler ratio WDTPS_16K_2 EQU 0XFD ; 1:16,384 WDTPS_8K_2 EQU 0XFB ; 1: 8,192 WDTPS_4K_2 EQU 0XF9 ; 1: 4,096 WDTPS_2K_2 EQU 0XF7 ; 1: 2,048 WDTPS_1K_2 EQU 0XF5 ; 1: 1,024 WDTPS_512_2 EQU 0XF3 ; 1: 512 WDTPS_256_2 EQU 0XF1 ; 1: 256 WDTPS_128_2 EQU 0XEF ; 1: 128 WDTPS_64_2 EQU 0XED ; 1: 64 WDTPS_32_2 EQU 0XEB ; 1: 32 WDTPS_16_2 EQU 0XE9 ; 1: 16 WDTPS_8_2 EQU 0XE7 ; 1: 8 WDTPS_4_2 EQU 0XE5 ; 1: 4 WDTPS_2_2 EQU 0XE3 ; 1: 2 WDTPS_1_2 EQU 0XE1 ; 1: 1 ;Configuration Byte 3H Options MCLRE_ON_3 EQU 0XFF ; MCLR enabled, RE3 input disabled MCLRE_OFF_3 EQU 0X7F ; MCLR disabled, RE3 input enabled ;Configuration Byte 4L Options DEBUG_ON_4 EQU 0X7F ; BacKground deBUGger enabled DEBUG_OFF_4 EQU 0XFF ; BacKground deBUGger disabled LVP_ON_4 EQU 0XFF ; Low Voltage Prgramming enabled LVP_OFF_4 EQU 0XFB ; Low Voltage Prgramming disabled STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enabled STVR_OFF_4 EQU 0XFE ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) CP0_ON_5 EQU 0XFE ; Block 0 protected CP0_OFF_5 EQU 0XFF ; Block 0 readable/ may be writable CP1_ON_5 EQU 0XFD ; Block 1 protected CP1_OFF_5 EQU 0XFF ; Block 1 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) CPB_ON_5 EQU 0XBF ; Boot Block protected CPB_OFF_5 EQU 0XFF ; Boot Block readable / may be writable CPD_ON_5 EQU 0X7F ; Data EE memory protected CPD_OFF_5 EQU 0XFF ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes WRT0_ON_6 EQU 0XFE ; Block 0 write protected WRT0_OFF_6 EQU 0XFF ; Block 0 writable WRT1_ON_6 EQU 0XFD ; Block 1 write protected WRT1_OFF_6 EQU 0XFF ; Block 1 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes WRTC_ON_6 EQU 0XDF ; Config registers write protected WRTC_OFF_6 EQU 0XFF ; Config registers writable WRTB_ON_6 EQU 0XBF ; Boot block write protected WRTB_OFF_6 EQU 0XFF ; Boot block writable WRTD_ON_6 EQU 0X7F ; Data EE write protected WRTD_OFF_6 EQU 0XFF ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks EBTR0_ON_7 EQU 0XFE ; Block 0 protected EBTR0_OFF_7 EQU 0XFF ; Block 0 readable EBTR1_ON_7 EQU 0XFD ; Block 1 protected EBTR1_OFF_7 EQU 0XFF ; Block 1 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks EBTRB_ON_7 EQU 0XBF ; Boot block read protected EBTRB_OFF_7 EQU 0XFF ; Boot block readable @ CONFIG_REQ @ __config CONFIG1H, HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, MCLRE_ON_3 @ __config CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f1320: ;Configuration Byte 1H Options IESO_ON_1 EQU 0XFF ; Internal External Oscillator Switch Over mode enabled IESO_OFF_1 EQU 0X7F ; Internal External Oscillator Switch Over mode disabled FSCMEN_ON_1 EQU 0XFF ; Fail Safe Clock Monitor enabled FSCMEN_OFF_1 EQU 0XBF ; Fail Safe Clock Monitor disabled RC_OSC_1 EQU 0XFF ; External RC on OSC1, OSC2 as Fosc/4 RCIO6_OSC_1 EQU 0XF7 ; External RC on OSC1, OSC2 as RA6 LP_OSC_1 EQU 0XF0 ; LP Oscillator XT_OSC_1 EQU 0XF1 ; XT Oscillator HS_OSC_1 EQU 0XF2 ; HS Oscillator HSPLL_OSC_1 EQU 0XF6 ; HS + PLL EC_OSC_1 EQU 0XF4 ; External Clock on OSC1, OSC2 as Fosc/4 ECIO6_OSC_1 EQU 0XF5 ; External Clock on OSC1, OSC2 as RA6 INTIO7_OSC_1 EQU 0XF9 ; Internal RC, OSC1 as RA7, OSC2 as Fosc/4 INTIO67_OSC_1 EQU 0XF8 ; Internal RC, OSC1 as RA7, OSC2 as RA6 ;Configuration Byte 2L Options BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v BOR_ON_2 EQU 0XFF ; Brown-Out Reset enabled BOR_OFF_2 EQU 0XFD ; Brown-Out Reset disabled PWRT_OFF_2 EQU 0XFF ; Power-Up Timer disabled PWRT_ON_2 EQU 0XFE ; Power-Up Timer enabled ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enabled WDT_OFF_2 EQU 0XFE ; Watch Dog Timer disabled WDTPS_32K_2 EQU 0XFF ; 1:32,768 WDT Postscaler ratio WDTPS_16K_2 EQU 0XFD ; 1:16,384 WDTPS_8K_2 EQU 0XFB ; 1: 8,192 WDTPS_4K_2 EQU 0XF9 ; 1: 4,096 WDTPS_2K_2 EQU 0XF7 ; 1: 2,048 WDTPS_1K_2 EQU 0XF5 ; 1: 1,024 WDTPS_512_2 EQU 0XF3 ; 1: 512 WDTPS_256_2 EQU 0XF1 ; 1: 256 WDTPS_128_2 EQU 0XEF ; 1: 128 WDTPS_64_2 EQU 0XED ; 1: 64 WDTPS_32_2 EQU 0XEB ; 1: 32 WDTPS_16_2 EQU 0XE9 ; 1: 16 WDTPS_8_2 EQU 0XE7 ; 1: 8 WDTPS_4_2 EQU 0XE5 ; 1: 4 WDTPS_2_2 EQU 0XE3 ; 1: 2 WDTPS_1_2 EQU 0XE1 ; 1: 1 ;Configuration Byte 3H Options MCLRE_ON_3 EQU 0XFF ; MCLR enabled, RE3 input disabled MCLRE_OFF_3 EQU 0X7F ; MCLR disabled, RE3 input enabled ;Configuration Byte 4L Options DEBUG_ON_4 EQU 0X7F ; BacKground deBUGger enabled DEBUG_OFF_4 EQU 0XFF ; BacKground deBUGger disabled LVP_ON_4 EQU 0XFF ; Low Voltage Prgramming enabled LVP_OFF_4 EQU 0XFB ; Low Voltage Prgramming disabled STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enabled STVR_OFF_4 EQU 0XFE ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) CP0_ON_5 EQU 0XFE ; Block 0 protected CP0_OFF_5 EQU 0XFF ; Block 0 readable/ may be writable CP1_ON_5 EQU 0XFD ; Block 1 protected CP1_OFF_5 EQU 0XFF ; Block 1 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) CPB_ON_5 EQU 0XBF ; Boot Block protected CPB_OFF_5 EQU 0XFF ; Boot Block readable / may be writable CPD_ON_5 EQU 0X7F ; Data EE memory protected CPD_OFF_5 EQU 0XFF ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes WRT0_ON_6 EQU 0XFE ; Block 0 write protected WRT0_OFF_6 EQU 0XFF ; Block 0 writable WRT1_ON_6 EQU 0XFD ; Block 1 write protected WRT1_OFF_6 EQU 0XFF ; Block 1 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes WRTC_ON_6 EQU 0XDF ; Config registers write protected WRTC_OFF_6 EQU 0XFF ; Config registers writable WRTB_ON_6 EQU 0XBF ; Boot block write protected WRTB_OFF_6 EQU 0XFF ; Boot block writable WRTD_ON_6 EQU 0X7F ; Data EE write protected WRTD_OFF_6 EQU 0XFF ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks EBTR0_ON_7 EQU 0XFE ; Block 0 protected EBTR0_OFF_7 EQU 0XFF ; Block 0 readable EBTR1_ON_7 EQU 0XFD ; Block 1 protected EBTR1_OFF_7 EQU 0XFF ; Block 1 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks EBTRB_ON_7 EQU 0XBF ; Boot block read protected EBTRB_OFF_7 EQU 0XFF ; Boot block readable @ CONFIG_REQ @ __config CONFIG1H, HS_OSC_1 @ __config CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_OFF_2 & WDTPS_128_2 @ __config CONFIG3H, MCLRE_ON_3 @ __config CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f2220: ;Configuration Byte 1H Options IESO_ON_1 EQU 0XFF ; Internal External Oscillator Switch Over mode enabled IESO_OFF_1 EQU 0X7F ; Internal External Oscillator Switch Over mode disabled FSCMEN_ON_1 EQU 0XFF ; Fail Safe Clock Monitor enabled FSCMEN_OFF_1 EQU 0XBF ; Fail Safe Clock Monitor disabled RC_OSC_1 EQU 0XFF ; External RC on OSC1, OSC2 as Fosc/4 RCIO_OSC_1 EQU 0XF7 ; External RC on OSC1, OSC2 as RA6 LP_OSC_1 EQU 0XF0 ; LP Oscillator XT_OSC_1 EQU 0XF1 ; XT Oscillator HS_OSC_1 EQU 0XF2 ; HS Oscillator HSPLL_OSC_1 EQU 0XF6 ; HS + PLL EC_OSC_1 EQU 0XF4 ; External Clock on OSC1, OSC2 as Fosc/4 ECIO_OSC_1 EQU 0XF5 ; External Clock on OSC1, OSC2 as RA6 INTIO1_OSC_1 EQU 0XF9 ; Internal RC, OSC1 as RA7, OSC2 as Fosc/4 INTIO2_OSC_1 EQU 0XF8 ; Internal RC, OSC1 as RA7, OSC2 as RA6 RCIO6_OSC_1 EQU 0XF7 ; compatabilty - RCIO new - BD 9/27/02 ECIO6_OSC_1 EQU 0XF5 ; compatabilty - ECIO new - BD 9/27/02 INTIO7_OSC_1 EQU 0XF9 ; compatabilty - INTIO1 new - BD 9/27/02 INTIO67_OSC_1 EQU 0XF8 ; compatabilty - INTIO2 new - BD 9/27/02 ;Configuration Byte 2L Options BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v BOR_ON_2 EQU 0XFF ; Brown-Out Reset enabled BOR_OFF_2 EQU 0XFD ; Brown-Out Reset disabled PWRT_OFF_2 EQU 0XFF ; Power-Up Timer disabled PWRT_ON_2 EQU 0XFE ; Power-Up Timer enabled ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enabled WDT_OFF_2 EQU 0XFE ; Watch Dog Timer disabled WDTPS_32K_2 EQU 0XFF ; 1:32,768 WDT Postscaler ratio WDTPS_16K_2 EQU 0XFD ; 1:16,384 WDTPS_8K_2 EQU 0XFB ; 1: 8,192 WDTPS_4K_2 EQU 0XF9 ; 1: 4,096 WDTPS_2K_2 EQU 0XF7 ; 1: 2,048 WDTPS_1K_2 EQU 0XF5 ; 1: 1,024 WDTPS_512_2 EQU 0XF3 ; 1: 512 WDTPS_256_2 EQU 0XF1 ; 1: 256 WDTPS_128_2 EQU 0XEF ; 1: 128 WDTPS_64_2 EQU 0XED ; 1: 64 WDTPS_32_2 EQU 0XEB ; 1: 32 WDTPS_16_2 EQU 0XE9 ; 1: 16 WDTPS_8_2 EQU 0XE7 ; 1: 8 WDTPS_4_2 EQU 0XE5 ; 1: 4 WDTPS_2_2 EQU 0XE3 ; 1: 2 WDTPS_1_2 EQU 0XE1 ; 1: 1 ;Configuration Byte 3L Options MCLRE_ON_3 EQU 0XFF ; MCLR enabled, RE3 input disabled MCLRE_OFF_3 EQU 0X7F ; MCLR disabled, RE3 input enabled PBAD_ANA_3 EQU 0XFF ; PORTB<4:0> pins reset as analog pins PBAD_DIG_3 EQU 0XFD ; PORTB<4:0> pins reset as digital pins incorrect bit was cleared - BD 5/30/2002 CCP2MX_ON_3 EQU 0XFF ; CCP2 pin function on RC1 CCP2MX_OFF_3 EQU 0XFE ; CCP2 pin function on RB3 CCP2MX_C1_3 EQU 0XFF ; CCP2 pin function on RC1 (alt defn) CCP2MX_B3_3 EQU 0XFE ; CCP2 pin function on RB3 (alt defn) ;Configuration Byte 4L Options DEBUG_ON_4 EQU 0X7F ; BacKground deBUGger enabled DEBUG_OFF_4 EQU 0XFF ; BacKground deBUGger disabled LVP_ON_4 EQU 0XFF ; Low Voltage Prgramming enabled LVP_OFF_4 EQU 0XFB ; Low Voltage Prgramming disabled STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enabled STVR_OFF_4 EQU 0XFE ; Stack over/underflow Reset disabled BKBUG_ON_4 EQU 0X7F ; compatabilty - DEBUG new - BD 9/27/02 BKBUG_OFF_4 EQU 0XFF ; compatabilty - DEBUG new - BD 9/27/02 ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) CP0_ON_5 EQU 0XFE ; Block 0 protected CP0_OFF_5 EQU 0XFF ; Block 0 readable/ may be writable CP1_ON_5 EQU 0XFD ; Block 1 protected CP1_OFF_5 EQU 0XFF ; Block 1 readable/ may be writable CP2_ON_5 EQU 0XFB ; Block 2 protected CP2_OFF_5 EQU 0XFF ; Block 2 readable/ may be writable CP3_ON_5 EQU 0XF7 ; Block 3 protected CP3_OFF_5 EQU 0XFF ; Block 3 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) CPB_ON_5H EQU 0XBF ; Boot Block protected CPB_OFF_5 EQU 0XFF ; Boot Block readable / may be writable CPD_ON_5 EQU 0X7F ; Data EE memory protected CPD_OFF_5 EQU 0XFF ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes WRT0_ON_6 EQU 0XFE ; Block 0 write protected WRT0_OFF_6 EQU 0XFF ; Block 0 writable WRT1_ON_6 EQU 0XFD ; Block 1 write protected WRT1_OFF_6 EQU 0XFF ; Block 1 writable WRT2_ON_6 EQU 0XFB ; Block 2 write protected WRT2_OFF_6 EQU 0XFF ; Block 2 writable WRT3_ON_6 EQU 0XF7 ; Block 3 write protected WRT3_OFF_6 EQU 0XFF ; Block 3 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes WRTC_ON_6 EQU 0XDF ; Config registers write protected WRTC_OFF_6 EQU 0XFF ; Config registers writable WRTB_ON_6 EQU 0XBF ; Boot block write protected WRTB_OFF_6 EQU 0XFF ; Boot block writable WRTD_ON_6 EQU 0X7F ; Data EE write protected WRTD_OFF_6 EQU 0XFF ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks EBTR0_ON_7 EQU 0XFE ; Block 0 protected EBTR0_OFF_7 EQU 0XFF ; Block 0 readable EBTR1_ON_7 EQU 0XFD ; Block 1 protected EBTR1_OFF_7 EQU 0XFF ; Block 1 readable EBTR2_ON_7 EQU 0XFB ; Block 2 protected EBTR2_OFF_7 EQU 0XFF ; Block 2 readable EBTR3_ON_7 EQU 0XF7 ; Block 3 protected EBTR3_OFF_7 EQU 0XFF ; Block 3 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU 0XBF ; Boot block read protected _EBTRB_OFF_7H EQU 0XFF ; Boot block readable @ CONFIG_REQ @ __config CONFIG1, HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, MCLRE_ON_3 & PBAD_DIG_3 @ __config CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f2320: ;Configuration Byte 1H Options IESO_ON_1 EQU 0XFF ; Internal External Oscillator Switch Over mode enabled IESO_OFF_1 EQU 0X7F ; Internal External Oscillator Switch Over mode disabled FSCMEN_ON_1 EQU 0XFF ; Fail Safe Clock Monitor enabled FSCMEN_OFF_1 EQU 0XBF ; Fail Safe Clock Monitor disabled RC_OSC_1 EQU 0XFF ; External RC on OSC1, OSC2 as Fosc/4 RCIO_OSC_1 EQU 0XF7 ; External RC on OSC1, OSC2 as RA6 LP_OSC_1 EQU 0XF0 ; LP Oscillator XT_OSC_1 EQU 0XF1 ; XT Oscillator HS_OSC_1 EQU 0XF2 ; HS Oscillator HSPLL_OSC_1 EQU 0XF6 ; HS + PLL EC_OSC_1 EQU 0XF4 ; External Clock on OSC1, OSC2 as Fosc/4 ECIO_OSC_1 EQU 0XF5 ; External Clock on OSC1, OSC2 as RA6 INTIO1_OSC_1 EQU 0XF9 ; Internal RC, OSC1 as RA7, OSC2 as Fosc/4 INTIO2_OSC_1 EQU 0XF8 ; Internal RC, OSC1 as RA7, OSC2 as RA6 RCIO6_OSC_1 EQU 0XF7 ; compatabilty - RCIO new - BD 9/27/02 ECIO6_OSC_1 EQU 0XF5 ; compatabilty - ECIO new - BD 9/27/02 INTIO7_OSC_1 EQU 0XF9 ; compatabilty - INTIO1 new - BD 9/27/02 INTIO67_OSC_1 EQU 0XF8 ; compatabilty - INTIO2 new - BD 9/27/02 ;Configuration Byte 2L Options BORV_20_2 EQU 0XFF ; BOR Voltage - 2.0v BORV_27_2 EQU 0XFB ; 2.7v BORV_42_2 EQU 0XF7 ; 4.2v BORV_45_2 EQU 0XF3 ; 4.5v BOR_ON_2 EQU 0XFF ; Brown-Out Reset enabled BOR_OFF_2 EQU 0XFD ; Brown-Out Reset disabled PWRT_OFF_2 EQU 0XFF ; Power-Up Timer disabled PWRT_ON_2 EQU 0XFE ; Power-Up Timer enabled ;Configuration Byte 2H Options WDT_ON_2 EQU 0XFF ; Watch Dog Timer enabled WDT_OFF_2 EQU 0XFE ; Watch Dog Timer disabled WDTPS_32K_2 EQU 0XFF ; 1:32,768 WDT Postscaler ratio WDTPS_16K_2 EQU 0XFD ; 1:16,384 WDTPS_8K_2 EQU 0XFB ; 1: 8,192 WDTPS_4K_2 EQU 0XF9 ; 1: 4,096 WDTPS_2K_2 EQU 0XF7 ; 1: 2,048 WDTPS_1K_2 EQU 0XF5 ; 1: 1,024 WDTPS_512_2 EQU 0XF3 ; 1: 512 WDTPS_256_2 EQU 0XF1 ; 1: 256 WDTPS_128_2 EQU 0XEF ; 1: 128 WDTPS_64_2 EQU 0XED ; 1: 64 WDTPS_32_2 EQU 0XEB ; 1: 32 WDTPS_16_2 EQU 0XE9 ; 1: 16 WDTPS_8_2 EQU 0XE7 ; 1: 8 WDTPS_4_2 EQU 0XE5 ; 1: 4 WDTPS_2_2 EQU 0XE3 ; 1: 2 WDTPS_1_2 EQU 0XE1 ; 1: 1 ;Configuration Byte 3H Options MCLRE_ON_3 EQU 0XFF ; MCLR enabled, RE3 input disabled MCLRE_OFF_3 EQU 0X7F ; MCLR disabled, RE3 input enabled PBAD_ANA_3 EQU 0XFF ; PORTB<4:0> pins reset as analog pins PBAD_DIG_3 EQU 0XFD ; PORTB<4:0> pins reset as digital pins incorrect bit was cleared - BD 5/30/2002 CCP2MX_ON_3 EQU 0XFF ; CCP2 pin function on RC1 CCP2MX_OFF_3 EQU 0XFE ; CCP2 pin function on RB3 CCP2MX_C1_3 EQU 0XFF ; CCP2 pin function on RC1 (alt defn) CCP2MX_B3_3 EQU 0XFE ; CCP2 pin function on RB3 (alt defn) ;Configuration Byte 4L Options DEBUG_ON_4 EQU 0X7F ; BacKground deBUGger enabled DEBUG_OFF_4 EQU 0XFF ; BacKground deBUGger disabled LVP_ON_4 EQU 0XFF ; Low Voltage Prgramming enabled LVP_OFF_4 EQU 0XFB ; Low Voltage Prgramming disabled STVR_ON_4 EQU 0XFF ; Stack over/underflow Reset enabled STVR_OFF_4 EQU 0XFE ; Stack over/underflow Reset disabled BKBUG_ON_4 EQU 0X7F ; compatabilty - DEBUG new - BD 9/27/02 BKBUG_OFF_4 EQU 0XFF ; compatabilty - DEBUG new - BD 9/27/02 ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) CP0_ON_5 EQU 0XFE ; Block 0 protected CP0_OFF_5 EQU 0XFF ; Block 0 readable/ may be writable CP1_ON_5 EQU 0XFD ; Block 1 protected CP1_OFF_5 EQU 0XFF ; Block 1 readable/ may be writable CP2_ON_5 EQU 0XFB ; Block 2 protected CP2_OFF_5 EQU 0XFF ; Block 2 readable/ may be writable CP3_ON_5 EQU 0XF7 ; Block 3 protected CP3_OFF_5 EQU 0XFF ; Block 3 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) CPB_ON_5H EQU 0XBF ; Boot Block protected CPB_OFF_5 EQU 0XFF ; Boot Block readable / may be writable CPD_ON_5 EQU 0X7F ; Data EE memory protected CPD_OFF_5 EQU 0XFF ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes WRT0_ON_6 EQU 0XFE ; Block 0 write protected WRT0_OFF_6 EQU 0XFF ; Block 0 writable WRT1_ON_6 EQU 0XFD ; Block 1 write protected WRT1_OFF_6 EQU 0XFF ; Block 1 writable WRT2_ON_6 EQU 0XFB ; Block 2 write protected WRT2_OFF_6 EQU 0XFF ; Block 2 writable WRT3_ON_6 EQU 0XF7 ; Block 3 write protected WRT3_OFF_6 EQU 0XFF ; Block 3 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes WRTC_ON_6 EQU 0XDF ; Config registers write protected WRTC_OFF_6 EQU 0XFF ; Config registers writable WRTB_ON_6 EQU 0XBF ; Boot block write protected WRTB_OFF_6 EQU 0XFF ; Boot block writable WRTD_ON_6 EQU 0X7F ; Data EE write protected WRTD_OFF_6 EQU 0XFF ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks EBTR0_ON_7 EQU 0XFE ; Block 0 protected EBTR0_OFF_7 EQU 0XFF ; Block 0 readable EBTR1_ON_7 EQU 0XFD ; Block 1 protected EBTR1_OFF_7 EQU 0XFF ; Block 1 readable EBTR2_ON_7 EQU 0XFB ; Block 2 protected EBTR2_OFF_7 EQU 0XFF ; Block 2 readable EBTR3_ON_7 EQU 0XF7 ; Block 3 protected EBTR3_OFF_7 EQU 0XFF ; Block 3 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU 0XBF ; Boot block read protected _EBTRB_OFF_7H EQU 0XFF ; Boot block readable @ CONFIG_REQ @ __config CONFIG1, HSPLL_OSC_1 @ __config CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, MCLRE_ON_3 & PBAD_DIG_3 @ __config CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f2331: ; CONFIG1H Options OSC_LP_1 EQU 0XF0 ; LP OSC_XT_1 EQU 0XF1 ; XT OSC_HS_1 EQU 0XF2 ; HS OSC_RC2_1 EQU 0XF3 ; External RC, RA6 is CLKOUT OSC_EC_1 EQU 0XF4 ; EC, RA6 is CLKOUT OSC_ECIO_1 EQU 0XF5 ; EC, RA6 is I/O OSC_HSPLL_1 EQU 0XF6 ; HS-PLL Enabled OSC_RCIO_1 EQU 0XF7 ; External RC, RA6 is I/O OSC_IRCIO_1 EQU 0XF8 ; Internal RC, RA6 & RA7 are I/O OSC_IRC_1 EQU 0XF9 ; Internal RC, RA6 is CLKOUT, RA7 is I/O OSC_RC1_1 EQU 0XFB ; External RC, RA6 is CLKOUT OSC_RC_1 EQU 0XFF ; External RC, RA6 is CLKOUT FCMEN_OFF_1 EQU 0XBF ; Disabled FCMEN_ON_1 EQU 0XFF ; Enabled IESO_OFF_1 EQU 0X7F ; Disabled IESO_ON_1 EQU 0XFF ; Enabled ; CONFIG2L Options PWRTEN_ON_2 EQU 0XFE ; Enabled PWRTEN_OFF_2 EQU 0XFF ; Disabled BOREN_OFF_2 EQU 0XFD ; Disabled BOREN_ON_2 EQU 0XFF ; Enabled BORV_45_2 EQU 0XF3 ; 4.5V BORV_42_2 EQU 0XF7 ; 4.2V BORV_27_2 EQU 0XFB ; 2.7V BORV_20_2 EQU 0XFF ; 2.0V ; CONFIG2H Options WDTEN_OFF_2 EQU 0XFE ; Disabled WDTEN_ON_2 EQU 0XFF ; Enabled WINEN_ON_2 EQU 0XDF ; Enabled WINEN_OFF_2 EQU 0XFF ; Disabled WDPS_1_2 EQU 0XE1 ; 1:1 WDPS_2_2 EQU 0XE3 ; 1:2 WDPS_4_2 EQU 0XE5 ; 1:4 WDPS_8_2 EQU 0XE7 ; 1:8 WDPS_16_2 EQU 0XE9 ; 1:16 WDPS_32_2 EQU 0XEB ; 1:32 WDPS_64_2 EQU 0XED ; 1:64 WDPS_128_2 EQU 0XEF ; 1:128 WDPS_256_2 EQU 0XF1 ; 1:256 WDPS_512_2 EQU 0XF3 ; 1:512 WDPS_1024_2 EQU 0XF5 ; 1:1024 WDPS_2048_2 EQU 0XF7 ; 1:2048 WDPS_4096_2 EQU 0XF9 ; 1:4096 WDPS_8192_2 EQU 0XFB ; 1:8192 WDPS_16384_2 EQU 0XFD ; 1:16384 WDPS_32768_2 EQU 0XFF ; 1:32768 ; CONFIG3L Options T1OSCMX_OFF_3 EQU 0XDF ; Active T1OSCMX_ON_3 EQU 0XFF ; Inactive HPOL_LOW_3 EQU 0XEF ; Active low HPOL_HIGH_3 EQU 0XFF ; Active high LPOL_LOW_3 EQU 0XF7 ; Active low LPOL_HIGH_3 EQU 0XFF ; Active high PWMPIN_ON_3 EQU 0XFB ; Enabled PWMPIN_OFF_3 EQU 0XFF ; Disabled ; CONFIG3H Options MCLRE_OFF_3 EQU 0X7F ; Disabled MCLRE_ON_3 EQU 0XFF ; Enabled EXCLKMX_RC3_3 EQU 0XEF ; MUXed with RC3 EXCLKMX_RD0_3 EQU 0XFF ; MUXed with RD0 PWM4MX_RD5_3 EQU 0XF7 ; MUXed with RD5 PWM4MX_RB5_3 EQU 0XFF ; MUXed with RB5 SSPMX_RC7_3 EQU 0XFB ; SD0 output muxed with RC7 SSPMX_RD1_3 EQU 0XFF ; SDO output muxed with RD1 FLTAMX_RD4_3 EQU 0XFE ; MUXed with RD4 FLTAMX_RC1_3 EQU 0XFF ; MUXed with RC1 ; CONFIG4L Options STVREN_OFF_4 EQU 0XFE ; Disabled STVREN_ON_4 EQU 0XFF ; Enabled LVP_OFF_4 EQU 0XFB ; Disabled LVP_ON_4 EQU 0XFF ; Enabled DEBUG_ON_4 EQU 0X7F ; Enabled DEBUG_OFF_4 EQU 0XFF ; Disabled ; CONFIG5L Options CP0_ON_5 EQU 0XFE ; Enabled CP0_OFF_5 EQU 0XFF ; Disabled CP1_ON_5 EQU 0XFD ; Enabled CP1_OFF_5 EQU 0XFF ; Disabled CP2_ON_5 EQU 0XFB ; Enabled CP2_OFF_5 EQU 0XFF ; Disabled CP3_ON_5 EQU 0XF7 ; Enabled CP3_OFF_5 EQU 0XFF ; Disabled ; CONFIG5H Options CPB_ON_5 EQU 0XBF ; Enabled CPB_OFF_5 EQU 0XFF ; Disabled CPD_ON_5 EQU 0X7F ; Enabled CPD_OFF_5 EQU 0XFF ; Disabled ; CONFIG6L Options WRT0_ON_6 EQU 0XFE ; Enabled WRT0_OFF_6 EQU 0XFF ; Disabled WRT1_ON_6 EQU 0XFD ; Enabled WRT1_OFF_6 EQU 0XFF ; Disabled WRT2_ON_6 EQU 0XFB ; Enabled WRT2_OFF_6 EQU 0XFF ; Disabled WRT3_ON_6 EQU 0XF7 ; Enabled WRT3_OFF_6 EQU 0XFF ; Disabled ; CONFIG6H Options WRTB_ON_6 EQU 0XBF ; Enabled WRTB_OFF_6 EQU 0XFF ; Disabled WRTC_ON_6 EQU 0XDF ; Enabled WRTC_OFF_6 EQU 0XFF ; Disabled WRTD_ON_6 EQU 0X7F ; Enabled WRTD_OFF_6 EQU 0XFF ; Disabled ; CONFIG7L Options EBTR0_ON_7 EQU 0XFE ; Enabled EBTR0_OFF_7 EQU 0XFF ; Disabled EBTR1_ON_7 EQU 0XFD ; Enabled EBTR1_OFF_7 EQU 0XFF ; Disabled EBTR2_ON_7 EQU 0XFB ; Enabled EBTR2_OFF_7 EQU 0XFF ; Disabled EBTR3_ON_7 EQU 0XF7 ; Enabled EBTR3_OFF_7 EQU 0XFF ; Disabled ; CONFIG7H Options EBTRB_ON_7 EQU 0XBF ; Enabled EBTRB_OFF_7 EQU 0XFF ; Disabled @ CONFIG_REQ @ __config CONFIG1H, OSC_HS_1 @ __config CONFIG2L, BOREN_ON_2 & BORV_20_2 & PWRTEN_ON_2 @ __config CONFIG2H, WDTEN_ON_2 & WDPS_128_2 @ __config CONFIG3H, MCLRE_ON_3 @ __config CONFIG4L, STVREN_ON_4 & LVP_OFF_4 & DEBUG_ON_4 18f2410: ; CONFIG1H Options OSC_LP_1 EQU 0XF0 ; LP OSC_XT_1 EQU 0XF1 ; XT OSC_HS_1 EQU 0XF2 ; HS OSC_RC_1 EQU 0XF3 ; RC OSC_EC_1 EQU 0XF4 ; EC-OSC2 as Clock Out OSC_ECIO6_1 EQU 0XF5 ; EC-OSC2 as RA6 OSC_HSPLL_1 EQU 0XF6 ; HS-PLL Enabled OSC_RCIO6_1 EQU 0XF7 ; RC-OSC2 as RA6 OSC_INTIO67_1 EQU 0XF8 ; INTRC-OSC2 as RA6, OSC1 as RA7 OSC_INTIO7_1 EQU 0XF9 ; INTRC-OSC2 as Clock Out, OSC1 as RA7 FCMEN_OFF_1 EQU 0XBF ; Disabled FCMEN_ON_1 EQU 0XFF ; Enabled IESO_OFF_1 EQU 0X7F ; Disabled IESO_ON_1 EQU 0XFF ; Enabled ; CONFIG2L Options PWRT_ON_2 EQU 0XFE ; Enabled PWRT_OFF_2 EQU 0XFF ; Disabled BOREN_OFF_2 EQU 0XF9 ; Disabled BOREN_ON_2 EQU 0XFB ; Enabled BOREN_NOSLP_2 EQU 0XFD ; Enabled except SLEEP, SBOREN Disabled BOREN_SBORDIS_2 EQU 0XFF ; Enabled, SBOREN Disabled BORV_45_2 EQU 0XE7 ; 4.5V BORV_42_2 EQU 0XEF ; 4.2V BORV_27_2 EQU 0XF7 ; 2.7V BORV_25_2 EQU 0XFF ; 2.5V ; CONFIG2H Options WDT_OFF_2 EQU 0XFE ; Disabled WDT_ON_2 EQU 0XFF ; Enabled WDTPS_1_2 EQU 0XE1 ; 1:1 WDTPS_2_2 EQU 0XE3 ; 1:2 WDTPS_4_2 EQU 0XE5 ; 1:4 WDTPS_8_2 EQU 0XE7 ; 1:8 WDTPS_16_2 EQU 0XE9 ; 1:16 WDTPS_32_2 EQU 0XEB ; 1:32 WDTPS_64_2 EQU 0XED ; 1:64 WDTPS_128_2 EQU 0XEF ; 1:128 WDTPS_256_2 EQU 0XF1 ; 1:256 WDTPS_512_2 EQU 0XF3 ; 1:512 WDTPS_1024_2 EQU 0XF5 ; 1:1024 WDTPS_2048_2 EQU 0XF7 ; 1:2048 WDTPS_4096_2 EQU 0XF9 ; 1:4096 WDTPS_8192_2 EQU 0XFB ; 1:8192 WDTPS_16384_2 EQU 0XFD ; 1:16384 WDTPS_32768_2 EQU 0XFF ; 1:32768 ; CONFIG3H Options MCLRE_OFF_3 EQU 0X7F ; Disabled MCLRE_ON_3 EQU 0XFF ; Enabled PBADEN_OFF_3 EQU 0XFD ; Port B<4:0> digital on RESET PBADEN_ON_3 EQU 0XFF ; Port B<4:0> analog on RESET CCP2MX_PORTBE_3 EQU 0XFE ; Muxed with RB3 CCP2MX_PORTC_3 EQU 0XFF ; Muxed with RC1 ; CONFIG4L Options STVREN_OFF_4 EQU 0XFE ; Disabled STVREN_ON_4 EQU 0XFF ; Enabled LVP_OFF_4 EQU 0XFB ; Disabled LVP_ON_4 EQU 0XFF ; Enabled ENHCPU_OFF_4 EQU 0X9F ; Disabled ENHCPU_ON_4 EQU 0XFF ; Enabled DEBUG_ON_4 EQU 0X7F ; Enabled DEBUG_OFF_4 EQU 0XFF ; Disabled ; CONFIG5L Options CP0_ON_5 EQU 0XFE ; Enabled CP0_OFF_5 EQU 0XFF ; Disabled CP1_ON_5 EQU 0XFD ; Enabled CP1_OFF_5 EQU 0XFF ; Disabled CP2_ON_5 EQU 0XFB ; Enabled CP2_OFF_5 EQU 0XFF ; Disabled CP3_ON_5 EQU 0XF7 ; Enabled CP3_OFF_5 EQU 0XFF ; Disabled ; CONFIG5H Options CPB_ON_5 EQU 0XBF ; Enabled CPB_OFF_5 EQU 0XFF ; Disabled ; CONFIG6L Options WRT0_ON_6 EQU 0XFE ; Enabled WRT0_OFF_6 EQU 0XFF ; Disabled WRT1_ON_6 EQU 0XFD ; Enabled WRT1_OFF_6 EQU 0XFF ; Disabled WRT2_ON_6 EQU 0XFB ; Enabled WRT2_OFF_6 EQU 0XFF ; Disabled WRT3_ON_6 EQU 0XF7 ; Enabled WRT3_OFF_6 EQU 0XFF ; Disabled ; CONFIG6H Options WRTB_ON_6 EQU 0XBF ; Enabled WRTB_OFF_6 EQU 0XFF ; Disabled WRTC_ON_6 EQU 0XDF ; Enabled WRTC_OFF_6 EQU 0XFF ; Disabled ; CONFIG7L Options EBTR0_ON_7 EQU 0XFE ; Enabled EBTR0_OFF_7 EQU 0XFF ; Disabled EBTR1_ON_7 EQU 0XFD ; Enabled EBTR1_OFF_7 EQU 0XFF ; Disabled EBTR2_ON_7 EQU 0XFB ; Enabled EBTR2_OFF_7 EQU 0XFF ; Disabled EBTR3_ON_7 EQU 0XF7 ; Enabled EBTR3_OFF_7 EQU 0XFF ; Disabled ; CONFIG7H Options EBTRB_ON_7 EQU 0XBF ; Enabled EBTRB_OFF_7 EQU 0XFF ; Disabled @ CONFIG_REQ @ __config CONFIG1H, OSC_HS_1 @ __config CONFIG2L, BOREN_ON_2 & BORV_25_2 & PWRT_ON_2 @ __config CONFIG2H, WDT_ON_2 & WDTPS_128_2 @ __config CONFIG3H, CCP2MX_PORTC_3 & PBADEN_OFF_3 @ __config CONFIG4L, STVREN_ON_4 & LVP_OFF_4 & ENHCPU_OFF_4 & DEBUG_ON_4 @ __config CONFIG5L, CP0_OFF_5 & CP1_OFF_5 & CP2_OFF_5 @ __config CONFIG5H, CPB_OFF_5 & CPB_OFF_5 @ __config CONFIG6L, WRT0_OFF_6 & WRT1_OFF_6 & WRT2_OFF_6 @ __config CONFIG6H, WRTC_OFF_6 & WRTB_OFF_6 @ __config CONFIG7L, EBTR0_OFF_7 & EBTR1_OFF_7 & EBTR2_OFF_7 @ __config CONFIG7H, EBTRB_OFF_7